US6336087B2
Expired / Lapsed
US
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Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debugging
Assignee: Mentor Graphics Corp
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Filing: 1998-07-24
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Granted: 2002-01-01
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Expires: 2018-07-24
Abstract
Abstract Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.
Inventors
- 👤 Luc M. Burgun
- 👤 Alain Raynaud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:39
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
105 words
A method comprising: receiving an original synthesizable register transfer level (RTL) source code; and synthesizing the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.
Claim 2
Independent Claim
105 words
A method comprising: receiving an original synthesizable register transfer level (RTL) source code; and synthesizing the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.
Claim 3
Dependent Claim
25 words
The method of claim 1 further comprising: synthesizing the original RTL source code to generate instrumentation information, wherein the instrumentation information comprises cross-reference instrumentation data.
Claim 4
Dependent Claim
25 words
The method of claim 1 wherein the gate-level representation of the original RTL source code and the instrumentation logic comprise a single gate-level design representation.
Claim 5
Dependent Claim
30 words
The method of claim 1 wherein synthesizing the original RTL source code to generate the gate-level representation and the instrumentation logic comprises modifying the RTL source code prior to synthesis.
Claim 6
Dependent Claim
24 words
The method of claim 1 wherein synthesizing the original RTL source code to generate the instrumentation logic comprises modifying a post parsed data structure.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein the original synthesizable RTL source code includes edge-sensitive statements.
Claim 8
Dependent Claim
16 words
The method of claim 1 wherein the original synthesizable RTL source code includes level sensitive statements.
Claim 9
Dependent Claim
37 words
The method of claim 1 further comprising: synthesizing the original RTL source code to generate instrumentation information, wherein the instrumentation information is generated for each of a list of synthesizable statements in the original RTL source code.
Claim 10
Dependent Claim
37 words
The method of claim 2 further comprising incrementing an execution count of the at least one synthesizable statement when cross reference instrumentation data of the corresponding instrumentation information indicates the at least one synthesizable statement is active.
Claim 11
Dependent Claim
36 words
The method of claim 1 further comprising displaying the at least one synthesizable statement as a highlighted statement during simulation in accordance with an execution status of the synthesizable statement as indicated by the instrumentation logic.
Claim 12
Dependent Claim
21 words
The method of claim 2 wherein the instrumentation information further utilizes selected logic of the gate-level representation of the RTL source.
Claim 13
Dependent Claim
121 words
A machine readable medium having stored therein machine executable instructions, wherein when executed the instructions enable the machine to: receive an original synthesizable register transfer level (RTL) source code; and synthesize the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.
Claim 14
Dependent Claim
121 words
A machine readable medium having stored therein machine executable instructions, wherein when executed the instructions enable the machine to: receive an original synthesizable register transfer level (RTL) source code; and synthesize the original RTL source code to generate a gate-level representation of the original RTL source code and also to generate instrumentation logic corresponding to at least one synthesizable statement in the original RTL source code, the instrumentation logic comprising logic circuitry in addition to logic circuitry of the gate-level representation of the original RTL source code, and the instrumentation logic to indicate an execution status of the at least one synthesizable statement of the original RTL source code during a gate-level simulation of the gate-level representation and the instrumentation logic.
Claim 15
Dependent Claim
33 words
The machine readable medium of claim 12 wherein the instructions further enable the machine to: synthesize the original RTL source code to generate instrumentation information, wherein the instrumentation information comprises cross-reference instrumentation data.
Claim 16
Dependent Claim
32 words
The machine readable medium of claim 12 wherein synthesizing the original RTL source code to generate the gate-level representation and the instrumentation logic comprises modifying the RTL source code prior to synthesis.
Claim 17
Dependent Claim
26 words
The machine readable medium of claim 12 wherein synthesizing the original RTL source code to generate the instrumentation logic comprises modifying a post parsed data structure.
Claim 18
Dependent Claim
45 words
The machine readable medium of claim 12 wherein the instructions further enable the machine to: synthesize the original RTL source code to generate instrumentation information, wherein the instrumentation information is generated for each of a list of synthesizable statements in the original RTL source code.
Claim 19
Dependent Claim
39 words
The machine readable medium of claim 13 further comprising incrementing an execution count of the at least one synthesizable statement when cross reference instrumentation data of the corresponding instrumentation information indicates the at least one synthesizable statement is active.
Claim 20
Dependent Claim
38 words
The machine readable medium of claim 12 further comprising displaying the at least one synthesizable statement as a highlighted statement during simulation in accordance with an execution status of the synthesizable statement as indicated by the instrumentation logic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-31 | 2005-07-02 | 2006-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-31 | 2009-07-02 | 2010-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-31 | 2013-07-02 | 2014-01-01 | $7700.00 | Window Closed / Lapsed |