Patent US6337284B1 successfully refreshed from Google Patents.
US6337284B1
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US
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Liquid crystal display device and method of manufacturing the same
Assignee: LG Display Co Ltd
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Filing: 2000-05-30
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Granted: 2002-01-08
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Expires: 2020-05-30
Abstract
Abstract The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode connecting with the drain electrode through the contact hole.
Inventors
- 👤 Kwangjo Hwang
- 👤 Changwook Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:14
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D86/40; H10D86/60; G02F1/1362; G02F1/136227; G02F1/136231
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
181 words
A method of manufacturing a liquid crystal display device, comprising: a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, a semiconductor layer, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a portion of the metal layer to produce a second photoresist pattern, thereby exposing the portion of the metal layer; and f) etching the gate insulating layer, the semiconductor layer, and the portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode connecting with the drain electrode through the contact hole.
Claim 2
Independent Claim
181 words
A method of manufacturing a liquid crystal display device, comprising: a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, a semiconductor layer, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a portion of the metal layer to produce a second photoresist pattern, thereby exposing the portion of the metal layer; and f) etching the gate insulating layer, the semiconductor layer, and the portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an ohmic contact layer, and an active area; a third photolithography process forming a passivation film and a contact hole; and a fourth photolithography process forming a pixel electrode connecting with the drain electrode through the contact hole.
Claim 3
Dependent Claim
16 words
The method of claim 1 , wherein the first etchant includes Cl 2 /O 2 gas.
Claim 4
Dependent Claim
15 words
The method of claim 2 , wherein the second etchant includes SF 6 /HCl gas.
Claim 5
Dependent Claim
18 words
The method of claim 2 , wherein the second etchant includes SF 6 /H 2 /Cl 2 gas.
Claim 6
Dependent Claim
16 words
The method of claim 1 , wherein the semiconductor layer includes first and second semiconductor layers.
Claim 7
Dependent Claim
14 words
The method of claim 5 , wherein the first semiconductor layer includes amorphous silicon.
Claim 8
Dependent Claim
15 words
The method of claim 5 , wherein the second semiconductor layer includes doped amorphous silicon.
Claim 9
Dependent Claim
29 words
The method of claim 1 , wherein the source and drain electrodes are made of a metal selected from a group consisting of Cr, Mo, Al, and Al alloy.
Claim 10
Dependent Claim
16 words
The method of claim 8 , wherein the semiconductor layer includes first and second semiconductor layers.
Claim 11
Dependent Claim
14 words
The method of claim 9 , wherein the first semiconductor layer includes amorphous silicon.
Claim 12
Dependent Claim
15 words
The method of claim 9 , wherein the second semiconductor layer includes doped amorphous silicon.
Claim 13
Dependent Claim
14 words
The method of claim 1 , wherein the pixel electrode includes indium tin oxide.
Claim 14
Dependent Claim
16 words
The method of claim 12 , wherein the semiconductor layer includes first and second semiconductor layers.
Claim 15
Dependent Claim
12 words
The method of claim 13 , first semiconductor layer includes amorphous silicon.
Claim 16
Dependent Claim
15 words
The method of claim 13 , wherein the second semiconductor layer includes doped amorphous silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-07 | 2005-07-09 | 2006-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-07 | 2009-07-09 | 2010-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-07 | 2013-07-09 | 2014-01-08 | $7700.00 | Window Closed / Lapsed |