Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores

Claim 1

A method for functional verification of circuit designs using reusable blocks or intellectual property cores, the method comprising steps of: providing one or more functional block or intellectual property core circuit design; generating from the provided function blocks or intellectual property core circuit designs a rule base; and verifying according to the rule base a functionality of an integrated circuit comprising the provided functional blocks or intellectual property core circuit designs, wherein the generating step comprises the steps of: categorizing one or more logic included in the provided functional blocks or intellectual property core circuit designs into a control, memory, register or datapath portion; and grouping logic of the control portion into a plurality of finite state machines (FSMS) in a manner that substantially minimizes a number of interactions among the FSMS.

Claim 2

A method for functional verification of circuit designs using reusable blocks or intellectual property cores, the method comprising steps of: providing one or more functional block or intellectual property core circuit design; generating from the provided function blocks or intellectual property core circuit designs a rule base; and verifying according to the rule base a functionality of an integrated circuit comprising the provided functional blocks or intellectual property core circuit designs, wherein the generating step comprises the steps of: categorizing one or more logic included in the provided functional blocks or intellectual property core circuit designs into a control, memory, register or datapath portion; and grouping logic of the control portion into a plurality of finite state machines (FSMS) in a manner that substantially minimizes a number of interactions among the FSMS.

Claim 7

A method for functionally verifying a design of a logic circuit comprising interacting logic including flip-flops, combinational logic and other logic that can be characterized as implementing finite state machines (FSMs), the method comprising the steps of: a. identifying a plurality of FSMs implemented by the other logic of the logic circuit; b. processing the design to determine for each identified FSM all states of the FSM that are reachable from an initial state of the FSM; c. processing the design to perform a simulation of logic circuit behavior and producing simulation results representing the logic circuit behavior; d. processing the simulation results to determine states visited by each remaining FSM; and e. comparing the visited states determined at step d to the reachable states determined at step b to determine whether any identified FSM failed to visit any of its reachable states during the simulation performed at step c.

Claim 8

A method for functionally verifying a design of a logic circuit comprising interacting logic including flip-flops, combinational logic and other logic that can be characterized as implementing finite state machines (FSMs), the method comprising the steps of: a. identifying a plurality of FSMs implemented by the other logic of the logic circuit; b. processing the design to determine for each identified FSM all states of the FSM that are reachable from an initial state of the FSM; c. processing the design to perform a simulation of logic circuit behavior and producing simulation results representing the logic circuit behavior; d. processing the simulation results to determine states visited by each remaining FSM; and e. comparing the visited states determined at step d to the reachable states determined at step b to determine whether any identified FSM failed to visit any of its reachable states during the simulation performed at step c.

Claim 15

A method of functionally verifying a design of a logic circuit comprising interacting logic including flip-flops and combinational logic and other logic that may be characterized as implementing finite state machines (FSMs), the method comprising the steps of: a. processing the design to identify a set of FSMs implemented by the other logic of the logic circuit; b. processing the design to compute a pair interaction strength for pairs of identified FSMs, wherein the pair interaction strength of each pair of FSMs is a number representing an estimate of a rate at which the FSMs of the pair are likely to interact with one another via signal paths therebetween; c. redefining a pair of the FSMs having a pair interaction strength within a particular range, along with any flip-flops or combinational logic in any signal path interconnecting the pair of identified FSMs, as being a single FSM, thereby to reduce a total number of identified FSMs by one; and d. repeating steps b and c until each identified FSM pair has a pair interaction strength within the particular range.

Claim 16

A method of functionally verifying a design of a logic circuit comprising interacting logic including flip-flops and combinational logic and other logic that may be characterized as implementing finite state machines (FSMs), the method comprising the steps of: a. processing the design to identify a set of FSMs implemented by the other logic of the logic circuit; b. processing the design to compute a pair interaction strength for pairs of identified FSMs, wherein the pair interaction strength of each pair of FSMs is a number representing an estimate of a rate at which the FSMs of the pair are likely to interact with one another via signal paths therebetween; c. redefining a pair of the FSMs having a pair interaction strength within a particular range, along with any flip-flops or combinational logic in any signal path interconnecting the pair of identified FSMs, as being a single FSM, thereby to reduce a total number of identified FSMs by one; and d. repeating steps b and c until each identified FSM pair has a pair interaction strength within the particular range.