Nonvolatile semiconductor memory

Claim 2

A semiconductor memory device comprising: a memory cell array in which cell transistors each having a charge accumulation layer are arranged in a matrix; and a potential supply circuit configured, at least in a read operation, to supply a potential different from a ground potential to gate of the cell transistors when the memory cell array is unselected.

Claim 3

The device according to claim 1 , further comprising: a latch circuit configured to latch data read out from the cell transistor, wherein after data read out from the cell transistor is latched by the latch circuit, the selection transistor coupled to the cell transistor from which the data is read out is unselected, and the potential different from the ground potential is supplied to the gate of the unselected cell transistor.

Claim 4

The device according to claim 1 , when the semiconductor memory is in a standby state, the potential different from the ground potential is supplied to the gate of the cell transistor.

Claim 5

The device according to claim 1 , wherein the potential different from the ground potential is a potential between maximum and minimum threshold voltages set for the cell transistor.

Claim 6

The device according to claim 1 , wherein the cell transistor stores bits of data as the threshold voltage of the cell transistor is changed.

Claim 7

The device according to claim 1 , wherein the potential different from the ground potential is positive potential higher than the ground potential.

Claim 8

The device according to claim 6 , wherein the cell transistor stores bits of data as a threshold voltage of the cell transistor is changed.

Claim 9

The device according to claim 7 , further comprising: a switch circuit configured to transfer the potential different from the ground potential, the switch circuit coupled between the cell transistor and the potential supply circuit.

Claim 10

The device according to claim 1 , further comprising: a plurality of memory cell arrays, each of the memory cell arrays including cell transistors arranged in a matrix, each of the cell transistors having a charge accumulation layer; and a decoding circuit for selecting at least one of the memory cell arrays and at least one of the cell transistors of the selected memory cell array.

Claim 11

The device according to claim 9 , wherein the potential different from the ground potential is a positive potential higher than the ground potential.

Claim 12

The device according to claim 10 , wherein the cell transistor stores bits of data as a threshold voltage of the cell transistor is changed.

Claim 13

A semiconductor memory device, comprising: a first block including a plurality of memory cell arrays, each of the plurality of memory cell arrays including cell transistors each having a charge accumulation layer and word lines coupled to gates of the cell transistors; a second block including a plurality of memory cell arrays, each of the plurality of memory cell arrays including cell transistors each having a charge accumulation layer and word lines coupled to gates of the cell transistors; a first circuit unit configured, at least in a read operation, to supply a potential different from a ground potential to the word lines of the first block when the first block is unselected; and a second circuit unit configured, at least in a read operation, to supply a potential different from a ground potential to the word lines of the second block when the second block is unselected.

Claim 14

A semiconductor memory device, comprising: a first block including a plurality of memory cell arrays, each of the plurality of memory cell arrays including cell transistors each having a charge accumulation layer and word lines coupled to gates of the cell transistors; a second block including a plurality of memory cell arrays, each of the plurality of memory cell arrays including cell transistors each having a charge accumulation layer and word lines coupled to gates of the cell transistors; a first circuit unit configured, at least in a read operation, to supply a potential different from a ground potential to the word lines of the first block when the first block is unselected; and a second circuit unit configured, at least in a read operation, to supply a potential different from a ground potential to the word lines of the second block when the second block is unselected.

Claim 15

The device according to claim 12 , wherein the first circuit unit includes a plurality of transistors connected to the word lines of the first block, the plurality of transistors of the first circuit unit are controlled by a first block selection signal, and second circuit unit includes a plurality of transistors connected to the word lines of the second block, the plurality of transistors of the second circuit unit are controlled by a second block selection signal.

Claim 16

The device according to claim 13 , further comprising: a bias circuit which generates the potential different from a ground potential, the bias circuit connected to the plurality of transistors of the first block and the plurality of transistors of the second block each connected to a bias circuit.