Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix each of which is capable of having n physical quantities (n≧3) to store one of n-levels, said memory cell array has a plurality of rows and a plurality of columns; first and second bitlines through which data is programmed to and read from one of said plurality of memory cells; a first data latch circuit for temporarily storing one of programming data and read data; a second data latch circuit for temporarily storing one of programming data and read data, said first bitline being selectively coupled to one of said first and second data latch circuits and said second bitline being selectively coupled to another one of said first and second data latch circuits; a column decoder for simultaneously selecting said plurality of columns and said first and second bitlines and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of columns; and a row decoder for simultaneously selecting said plurality of rows and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of rows.

Claim 3

The semiconductor memory device according to claim 1, wherein said data is one of a maximum level item corresponding to the maximum one of said n physical quantities and a minimum level item corresponding to the minimum one of said n physical quantities.

Claim 4

The semiconductor memory device according to claim 1, wherein said column decoder and said row decoder program predetermined data to said corresponding memory cells without an input of data to said semiconductor memory device.

Claim 5

The semiconductor memory device according to claim 1, wherein levels of programming data programmed in adjacent columns are different from each other in said n physical quantities.

Claim 6

The semiconductor memory device according to claim 4, wherein data of said corresponding memory cells is simultaneously erased.

Claim 7

The semiconductor memory device according to claim 5, wherein said erasing data is one of a maximum level item corresponding to the maximum one of said n physical quantities and a minimum level item corresponding to the minimum one of said n physical quantities.

Claim 8

The semiconductor memory device according to claim 1, wherein each of said plurality of memory cells has a floating gate and said physical quantity is a charge stored in said floating gate.

Claim 9

The semiconductor memory device according to claim 1, wherein each of said plurality of memory cells has a capacitor and said physical quantity is a charge stored in said capacitor.

Claim 10

The semiconductor memory device according to claim 1, wherein said column decoder and said row decoder program data to said corresponding memory cells by Fowler-Nordheim tunneling.

Claim 11

The semiconductor memory device according to claim 1, wherein said column decoder and said row decoder program data to said corresponding memory cells in accordance with a plurality of input addresses of said row decoder and a plurality of input addresses of said column decoder which are in a selected state.

Claim 12

The semiconductor memory device according to claim 1, wherein said row decoder and said column decoder simultaneously select said plurality of rows and said plurality of columns and subsequently simultaneously program data in said corresponding memory cells arranged in said plurality of rows and said plurality of columns during a test mode.

Claim 13

The semiconductor memory device of claim 1 further comprising a first precharger coupled to said first bitline for precharging said first bitline, and a second precharger coupled to said second bitline for precharging said second bitline.

Claim 14

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, wherein each cell is capable of storing one of n levels (n≧3); a plurality of bitlines connected to said memory cells, where each of said memory cells is connected to one of said bitlines; a column decoder for selecting a plurality of columns of said memory cells, and the bitlines connected to the memory cells in said selected plurality of columns, at one time, and programming corresponding memory cells arranged in said selected plurality of columns simultaneously; a row decoder for selecting a plurality of rows of said memory cells at one time and programming corresponding memory cells arranged in said selected plurality of rows simultaneously; and a plurality of data latch circuits connected to said bitlines for temporarily storing, at a particular time, either data read from said memory cells in a read operation or data to be written to said memory cells in a write operation.

Claim 15

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, wherein each cell is capable of storing one of n levels (n≧3); a plurality of bitlines connected to said memory cells, where each of said memory cells is connected to one of said bitlines; a column decoder for selecting a plurality of columns of said memory cells, and the bitlines connected to the memory cells in said selected plurality of columns, at one time, and programming corresponding memory cells arranged in said selected plurality of columns simultaneously; a row decoder for selecting a plurality of rows of said memory cells at one time and programming corresponding memory cells arranged in said selected plurality of rows simultaneously; and a plurality of data latch circuits connected to said bitlines for temporarily storing, at a particular time, either data read from said memory cells in a read operation or data to be written to said memory cells in a write operation.

Claim 16

The device of claim 13, wherein said selected plurality of rows is a sub-plurality of all rows of said matrix.

Claim 17

The device of claim 13, wherein said selected plurality of columns is a sub-plurality of all columns of said matrix.

Claim 18

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein each of said memory cells is capable of having n physical quantities (n≧3) to store one of n levels, said memory cell array having a plurality of rows and a plurality of columns; first and second bitlines, in which data is programmed to and read from one of said plurality of memory cells, selectively coupled to at least one of said first and second data latch circuits; first and second data latch circuits for temporarily storing one of programming data and read data read through at least one of said first and second bitlines; a first transfer gate coupled to said first bitline for connecting said first bitline with at least one of said first and second data latch circuits by a first signal; a second transfer gate coupled to said second bitline for connecting said second bitline with at least one of said first and second data latch circuits by a second signal; a column decoder for simultaneously selecting said plurality of columns and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of columns; and a row decoder for simultaneously selecting said plurality of rows and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of rows.

Claim 19

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein each of said memory cells is capable of having n physical quantities (n≧3) to store one of n levels, said memory cell array having a plurality of rows and a plurality of columns; first and second bitlines, in which data is programmed to and read from one of said plurality of memory cells, selectively coupled to at least one of said first and second data latch circuits; first and second data latch circuits for temporarily storing one of programming data and read data read through at least one of said first and second bitlines; a first transfer gate coupled to said first bitline for connecting said first bitline with at least one of said first and second data latch circuits by a first signal; a second transfer gate coupled to said second bitline for connecting said second bitline with at least one of said first and second data latch circuits by a second signal; a column decoder for simultaneously selecting said plurality of columns and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of columns; and a row decoder for simultaneously selecting said plurality of rows and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of rows.

Claim 20

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein each of said memory cells is capable of having n physical quantities (n≧3) to store one of n levels, said memory cell array having a plurality of rows and a plurality of columns; a plurality of data latch circuits for temporarily storing one of programming data and read data; a first bitline, through which data is programmed to and read from one of said plurality of memory cells, selectively coupled to one of said plurality of data latch circuits; a second bitline, through which data is programmed to and read from another one of said plurality of memory cells, selectively coupled to another one of said plurality of data latch circuits; a column decoder for simultaneously selecting said plurality of columns and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of columns; and a row decoder for simultaneously selecting said plurality of rows and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of rows.

Claim 21

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix, wherein each of said memory cells is capable of having n physical quantities (n≧3) to store one of n levels, said memory cell array having a plurality of rows and a plurality of columns; a plurality of data latch circuits for temporarily storing one of programming data and read data; a first bitline, through which data is programmed to and read from one of said plurality of memory cells, selectively coupled to one of said plurality of data latch circuits; a second bitline, through which data is programmed to and read from another one of said plurality of memory cells, selectively coupled to another one of said plurality of data latch circuits; a column decoder for simultaneously selecting said plurality of columns and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of columns; and a row decoder for simultaneously selecting said plurality of rows and subsequently simultaneously programming data in corresponding memory cells arranged in said plurality of rows.

Claim 22

The semiconductor memory device according to claim 17, wherein said plurality of data latch circuits consists of two data latch circuits.