Patent US6452860B2 successfully refreshed from Google Patents.
US6452860B2
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Semiconductor memory device having segment type word line structure
Assignee: Fujitsu Semiconductor Ltd
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Filing: 2001-06-04
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Granted: 2002-09-17
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Expires: 2021-06-04
Abstract
Abstract A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.
Inventors
- 👤 Masaharu Wada
- 👤 Kenji Tsuchida
- 👤 Tsuneo Inaba
- 👤 Atsushi Takeuchi
- 👤 Toshimi Ikeda
- 👤 Kuninori Kawabata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/06; G11C5/063
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
94 words
A semiconductor memory device which has a segment type word line structure and in which a plurality of main word lines and a plurality of sub word lines are arranged, the semiconductor memory device comprising: a memory cell array divided into a plurality of cell array blocks, between which sub row decoder areas are arranged; and a plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines, passing across the sub row decoder areas and arranged in common to the pluralit of cell array blocks.
Claim 2
Dependent Claim
94 words
A semiconductor memory device which has a segment type word line structure and in which a plurality of main word lines and a plurality of sub word lines are arranged, the semiconductor memory device comprising: a memory cell array divided into a plurality of cell array blocks, between which sub row decoder areas are arranged; and a plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines, passing across the sub row decoder areas and arranged in common to the pluralit of cell array blocks.
Claim 3
Dependent Claim
24 words
A semiconductor memory device according to claim 1 , wherein said plurality of first metal wiring lines are parallel to said main word lines.
Claim 4
Dependent Claim
29 words
A semiconductor memory device according to claim 1 , wherein each of the plurality of cell array blocks includes a plurality of memory cells arranged in a matrix pattern.
Claim 5
Dependent Claim
40 words
A semiconductor memory device according to claim 1 , wherein each of the sub row decoder areas is provided with a plurality of sub row decoders for selecting a specific sub word line from said plurality of sub word lines.
Claim 6
Dependent Claim
50 words
A semiconductor memory device according to claim 1 , further comprising a plurality of second metal wiring lines which are located at a level above said plurality of main word lines, said plurality of second metal wiring lines extending in a direction orthogonal to said plurality of main word lines.
Claim 7
Dependent Claim
34 words
A semiconductor memory device according to claim 5 , wherein said plurality of second metal wiring lines are connected to said plurality of first metal wiring lines by way of a plurality of contacts.
Claim 8
Dependent Claim
20 words
A semiconductor memory device according to claim 1 , further comprising a capacitor array provided with a plurality of capacitors.
Claim 9
Dependent Claim
43 words
A semiconductor memory device according to claim 7 , wherein each of said plurality of capacitors is connected to wiring lines which are included among said first metal wiring lines and which are used as a power supply line and a grounding line.
Claim 10
Dependent Claim
27 words
A semiconductor memory device according to claim 8 , wherein each of said capacitors serves to bypass noise between the power supply line and the grounding line.
Claim 11
Dependent Claim
20 words
A semiconductor memory device according to claim 7 , wherein each of said plurality of capacitors is an MOS capacitor.
Claim 12
Dependent Claim
27 words
A semiconductor memory device according to claim 7 , wherein said capacitor array includes blocks which are similar in configuration to said plurality of cell array blocks.
Claim 13
Dependent Claim
48 words
A semiconductor memory device according to claim 11 , wherein each of the memory cell array blocks includes a plurality of memory cells arranged in a matrix pattern and wherein said plurality of capacitors are memory cells which are similar in structure to said plurality of memory cells.
Claim 14
Dependent Claim
36 words
A semiconductor memory device according to claim 12 , wherein said plurality of capacitors are dynamic memory cells each including a cell capacitor and a cell transistor, and said cell transistor is in a normally-ON state.
Claim 15
Dependent Claim
40 words
A semiconductor memory device according to claim 1 , wherein said plurality of cell array blocks constitute a plurality of memory banks, and said plurality of first metal wiring lines are provided in common to said plurality of memory banks.
Claim 16
Dependent Claim
36 words
A semiconductor memory device according to claim 14 , wherein said plurality of memory banks are spaced apart by main row decoder areas, and said first metal wiring lines extend across the main row decoder areas.
Claim 17
Dependent Claim
45 words
A semiconductor memory device according to claim 15 , wherein each of said main row decoder areas is provided with a plurality of main row decoders, each of the main row decoders selecting a specific main word line from said plurality of main word lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-16 | 2006-03-18 | 2006-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-16 | 2010-03-18 | 2010-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-16 | 2014-03-18 | 2014-09-17 | $7700.00 | Window Closed / Lapsed |