Patent US6468896B2 successfully refreshed from Google Patents.
US6468896B2
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Method of fabricating semiconductor components
Assignee: Siemens AG
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Filing: 2000-12-29
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Granted: 2002-10-22
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Expires: 2020-12-29
Abstract
Abstract Disclosed is a method for producing semiconductor elements including a metal layer ( 10 ) configured on a semiconductor substrate ( 5 ). The inventive method consists of the following steps: a silicon layer ( 15 ) is deposited on a metal layer ( 10 ); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched ( 15 ) using the etch mask ( 25 ); and the metal layer ( 10 ) is structured in an etching process using a selectively etched silicon layer ( 15 ) as a hard mask.
Inventors
- 👤 Thomas Röhr
- 👤 Christine Dehm
- 👤 Carlos Mazure-Espejo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:28
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10P; H10P50/00; H10P50/71; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/95
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
70 words
A method for fabricating semiconductor components having an electrically conductive layer configured on a semiconductor substrate, which comprises: applying a silicon mask layer to a conductive layer; applying an etching mask to the conductive layer for patterning the silicon mask layer; selectively etching the silicon mask layer using the etching mask; and patterning the conductive layer in an etching process using the selectively etched mask layer as a hard mask.
Claim 2
Independent Claim
70 words
A method for fabricating semiconductor components having an electrically conductive layer configured on a semiconductor substrate, which comprises: applying a silicon mask layer to a conductive layer; applying an etching mask to the conductive layer for patterning the silicon mask layer; selectively etching the silicon mask layer using the etching mask; and patterning the conductive layer in an etching process using the selectively etched mask layer as a hard mask.
Claim 3
Dependent Claim
47 words
The method according to claim 1 , which comprises: leaving the silicon mask layer on the conductive layer after the conductive layer has been patterned; and using the silicon mask layer as an adhesion promoting layer between the conductive layer and a further layer that is deposited.
Claim 4
Dependent Claim
27 words
The method according to claim 1 , which comprises adapting a thickness of the silicon mask layer to reduce reflections during photolithographic patterning of its etching mask.
Claim 5
Dependent Claim
22 words
The method according to claim 1 , which comprises using the silicon layer as an etching stop for protecting the conductive layer.
Claim 6
Dependent Claim
27 words
The method according to claim 1 , wherein the silicon layer is a layer selected from the group consisting of an amorphous layer and a polycrystalline layer.
Claim 7
Dependent Claim
13 words
The method according to claim 1 , which comprises doping the silicon layer.
Claim 8
Dependent Claim
31 words
The method according to claim 1 , which comprises using the silicon layer as a hard mask while selectively etching a layer sequence which includes the conductive layer and a dielectric.
Claim 9
Dependent Claim
17 words
The method according to claim 1 , which comprises using a metal layer as the conductive layer.
Claim 10
Dependent Claim
25 words
The method according to claim 8 , wherein the metal layer includes a metal selected from the group consisting of platinum, iridium, palladium, and ruthenium.
Claim 11
Dependent Claim
25 words
The method according to claim 1 , wherein the conductive layer is a layer selected from the group consisting of iridium oxide and ruthenium oxide.
Claim 12
Dependent Claim
106 words
A semiconductor component comprising: a semiconductor substrate; a conductive layer configured on said semiconductor substrate; a mask layer covering said conductive layer, said mask layer being a silicon layer; and a further layer configured above said conductive layer and connected to said conductive layer with said mask layer interposed therebetween, said further layer having a contact hole therethrough for making contact with said conductive layer, said contact hole extending at least to said mask layer; said conductive layer being a layer selected from the group consisting of platinum, iridium, palladium, ruthenium, an alloy of at least one of the abovementioned metals, iridium oxide, and ruthenium oxide.
Claim 13
Dependent Claim
106 words
A semiconductor component comprising: a semiconductor substrate; a conductive layer configured on said semiconductor substrate; a mask layer covering said conductive layer, said mask layer being a silicon layer; and a further layer configured above said conductive layer and connected to said conductive layer with said mask layer interposed therebetween, said further layer having a contact hole therethrough for making contact with said conductive layer, said contact hole extending at least to said mask layer; said conductive layer being a layer selected from the group consisting of platinum, iridium, palladium, ruthenium, an alloy of at least one of the abovementioned metals, iridium oxide, and ruthenium oxide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |