Patent US6514672B2 successfully refreshed from Google Patents.
US6514672B2
Expired / Lapsed
US
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Dry development process for a bi-layer resist system
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2001-06-11
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Granted: 2003-02-04
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Expires: 2021-06-11
Abstract
Abstract A new method of forming a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first planarized photoresist layer which is baked. The first photoresist layer is coated with a second silicon-containing photoresist layer which is baked. Portions of the second photoresist layer not covered by a mask are exposed to actinic light. The exposed portions of the second photoresist layer are developed away. Then, portions of the first photoresist layer not covered by the second photoresist layer remaining are developed away in a dry development step wherein sufficient SO 2 gas is included in the developing recipe to reduce microloading to form a bi-layer photoresist mask comprising the first and second photoresist layers remaining. Thereafter, the bi-layer photoresist mask is ashed to smooth its sidewall edges. This completes formation of a bi-layer photoresist mask having a reduced critical dimension bias between isolated and dense lines and reduced edge roughness.
Inventors
- 👤 Bao-Ju Young
- 👤 Chia-Shiung Tsai
- 👤 Ying-Ying Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:08
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/26; G03F7/36
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
204 words
A method of providing a uniform critical dimension during photoetching in the fabrication of an integrated circuit comprising: providing a layer to be etched on a semiconductor substrate wherein the surface of said layer has an uneven topography; coating said layer to be etched with a first photoresist layer wherein said first photoresist layer is planarized; baking said first photoresist layer; coating said first photoresist layer with a second silicon-containing photoresist layer; baking said second photoresist layer; exposing portions of said second photoresist layer not covered by a mask to actinic light; first developing away said exposed portions of said second photoresist layer; second developing away portions of said first photoresist layer not covered by said second photoresist layer remaining wherein sufficient SO 2 gas is included in said second developing to reduce microloading to form a bi-layer photoresist mask comprising said first and second photoresist layers remaining; thereafter ashing said bi-layer photoresist mask to smooth the sidewall edges of said bi-layer photoresist mask; thereafter etching away said layer to be etched where it is not covered by said bi-layer photoresist mask; and removing said bi-layer photoresist mask to complete said photoetching having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 2
Independent Claim
204 words
A method of providing a uniform critical dimension during photoetching in the fabrication of an integrated circuit comprising: providing a layer to be etched on a semiconductor substrate wherein the surface of said layer has an uneven topography; coating said layer to be etched with a first photoresist layer wherein said first photoresist layer is planarized; baking said first photoresist layer; coating said first photoresist layer with a second silicon-containing photoresist layer; baking said second photoresist layer; exposing portions of said second photoresist layer not covered by a mask to actinic light; first developing away said exposed portions of said second photoresist layer; second developing away portions of said first photoresist layer not covered by said second photoresist layer remaining wherein sufficient SO 2 gas is included in said second developing to reduce microloading to form a bi-layer photoresist mask comprising said first and second photoresist layers remaining; thereafter ashing said bi-layer photoresist mask to smooth the sidewall edges of said bi-layer photoresist mask; thereafter etching away said layer to be etched where it is not covered by said bi-layer photoresist mask; and removing said bi-layer photoresist mask to complete said photoetching having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 3
Dependent Claim
28 words
The method according to claim 1 wherein said first photoresist layer comprises an acrylic polymer and is coated to a thickness of between about 4000 and 5000 Angstroms.
Claim 4
Dependent Claim
28 words
The method according to claim 1 wherein said first photoresist layer is baked at a temperature of between about 120 and 130° C. for 2 to 3 minutes.
Claim 5
Dependent Claim
28 words
The method according to claim 1 wherein said second photoresist layer comprises a silicon-containing monomer and is coated to a thickness of between about 2000 and 3000 Angstroms.
Claim 6
Dependent Claim
28 words
The method according to claim 1 wherein said second photoresist layer is baked at a temperature of between about 120 and 130° C. for 2 to 3 minutes.
Claim 7
Dependent Claim
69 words
The method according to claim 1 wherein said step of second developing away comprises flowing O 2 gas at between about 30 and 40 sccm, flowing He at between about 50 and 60 sccm, and flowing SO 2 at between about 60 and 70 sccm at a pressure of 5 to 6 mTorr and top power of 400 to 500 watts and bottom power of 120 to 130 watts.
Claim 8
Dependent Claim
58 words
The method according to claim 1 wherein said step of ashing comprises flowing HBr gas at between about 30 and 40 sccm and flowing O 2 gas at between about 10 and 20 sccm at a pressure of 5 to 6 mTorr and top power of 270 to 210 watts and bottom power of 120 to 130 watts.
Claim 9
Independent Claim
223 words
A method of providing a uniform critical dimension during photoetching in the fabrication of an integrated circuit comprising: providing a layer to be etched on a semiconductor substrate wherein the surface of said layer has an uneven topography; coating said layer to be etched with a first photoresist layer wherein said first photoresist layer is planarized; baking said first photoresist layer; coating said first photoresist layer with a second photoresist layer and silylating said second photoresist layer to form a silicon-containing photoresist layer; baking said silicon-containing photoresist layer; exposing portions of said silicon-containing photoresist layer not covered by a mask to actinic light; first developing away said exposed portions of said silicon-containing photoresist layer; second developing away portions of said first photoresist layer not covered by said silicon-containing photoresist layer remaining wherein sufficient SO 2 gas is flowed at between about 60 and 70 sccm in said second developing to reduce microloading to form a bi-layer photoresist mask comprising said first and second silicon-containing photoresist layers remaining; thereafter ashing said bi-layer photoresist mask to smooth the sidewall edges of said bi-layer photoresist mask; thereafter etching away said layer to be etched where it is not covered by said bi-layer photoresist mask; and removing said bi-layer photoresist mask to complete said photoetching having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 10
Independent Claim
223 words
A method of providing a uniform critical dimension during photoetching in the fabrication of an integrated circuit comprising: providing a layer to be etched on a semiconductor substrate wherein the surface of said layer has an uneven topography; coating said layer to be etched with a first photoresist layer wherein said first photoresist layer is planarized; baking said first photoresist layer; coating said first photoresist layer with a second photoresist layer and silylating said second photoresist layer to form a silicon-containing photoresist layer; baking said silicon-containing photoresist layer; exposing portions of said silicon-containing photoresist layer not covered by a mask to actinic light; first developing away said exposed portions of said silicon-containing photoresist layer; second developing away portions of said first photoresist layer not covered by said silicon-containing photoresist layer remaining wherein sufficient SO 2 gas is flowed at between about 60 and 70 sccm in said second developing to reduce microloading to form a bi-layer photoresist mask comprising said first and second silicon-containing photoresist layers remaining; thereafter ashing said bi-layer photoresist mask to smooth the sidewall edges of said bi-layer photoresist mask; thereafter etching away said layer to be etched where it is not covered by said bi-layer photoresist mask; and removing said bi-layer photoresist mask to complete said photoetching having said uniform critical dimension in the fabrication of said integrated circuit.
Claim 11
Dependent Claim
28 words
The method according to claim 8 wherein said first photoresist layer comprises an acrylic polymer and is coated to a thickness of between about 4000 and 5000 Angstroms.
Claim 12
Dependent Claim
28 words
The method according to claim 8 wherein said first photoresist layer is baked at a temperature of between about 120 and 130° C. for 2 to 3 minutes.
Claim 13
Dependent Claim
28 words
The method according to claim 8 wherein said second photoresist layer comprises a silicon-containing monomer and is coated to a thickness of between about 2000 and 3000 Angstroms.
Claim 14
Dependent Claim
69 words
The method according to claim 8 wherein said step of second developing away comprises flowing O 2 gas at between about 30 and 40 sccm, flowing He at between about 50 and 60 sccm, and flowing SO 2 at between about 60 and 70 sccm at a pressure of 5 to 6 mTorr and top power of 400 to 500 watts and bottom power of 120 to 130 watts.
Claim 15
Dependent Claim
58 words
The method according to claim 8 wherein said step of ashing comprises flowing HBr gas at between about 30 and 40 sccm and flowing O 2 gas at between about 10 and 20 sccm at a pressure of 5 to 6 mTorr and top power of 270 to 280 watts and bottom power of 120 to 130 watts.
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