Word-line driving circuit with reduced current leakage

Claim 3

The method of claim 1 , wherein driving the plurality of the word lines simultaneously to the erasing potential comprises driving all of the word lines in the non-volatile semiconductor memory simultaneously to the erasing potential.

Claim 4

The method of claim 2 , wherein supplying the mitigating potential comprises supplying a chip erase signal to the respective switching elements.

Claim 5

The method of claim 3 , wherein supplying the ground potential also comprises supplying the chip erase signal to the respective switching elements.

Claim 6

The method of claim 1 , wherein driving the plurality of the word lines simultaneously to the erasing potential comprises: selecting a block of the word lines according to an address signal; and driving the word lines in the selected block to the erasing potential.

Claim 7

The method of claim 5 , wherein supplying the mitigating potential comprises: performing a logic operation on at least the address signal and a block erase signal to generate a selection signal; and supplying the selection signal to the respective switching elements.

Claim 8

The method of claim 6 , wherein supplying the ground potential also comprises supplying the selection signal to the respective switching elements.

Claim 9

The method of claim 1 , further comprising: generating the erasing potential by level-shifting a write control signal; generating a reading potential by logic operations without level shifting; and driving the word lines to the reading potential to read the data stored in the coupled memory cells.

Claim 10

A word-line driving circuit for a non-volatile semiconductor memory having a plurality of word lines and a plurality of memory cells coupled to the word lines, the non-volatile semiconductor memory being operable in a write mode to store data in the memory cells, a read mode to read the stored data, and a first erase mode to simultaneously erase the data stored in the memory cells coupled to at least two of the word lines, the word-line driving circuit comprising: a plurality of first switching elements coupled to respective word lines; a plurality of second switching elements coupled to respective word lines; first means for switching the first switching elements and the second switching elements on and off; second means for supplying the first switching elements with different potentials for driving the word lines, the different potentials including at least an erasing potential supplied in the first erase mode; and third means for supplying the second switching elements with a ground potential in the write mode and the read mode, and with a mitigating potential in the first erase mode, the mitigating potential being intermediate between the ground potential and the erasing potential.

Claim 11

A word-line driving circuit for a non-volatile semiconductor memory having a plurality of word lines and a plurality of memory cells coupled to the word lines, the non-volatile semiconductor memory being operable in a write mode to store data in the memory cells, a read mode to read the stored data, and a first erase mode to simultaneously erase the data stored in the memory cells coupled to at least two of the word lines, the word-line driving circuit comprising: a plurality of first switching elements coupled to respective word lines; a plurality of second switching elements coupled to respective word lines; first means for switching the first switching elements and the second switching elements on and off; second means for supplying the first switching elements with different potentials for driving the word lines, the different potentials including at least an erasing potential supplied in the first erase mode; and third means for supplying the second switching elements with a ground potential in the write mode and the read mode, and with a mitigating potential in the first erase mode, the mitigating potential being intermediate between the ground potential and the erasing potential.

Claim 12

The word-line driving circuit of claim 9 , wherein, in the first erase mode, the first means switches on all of the first switching elements and switches off all of the second switching elements, thereby driving all of the word lines to the erasing potential.

Claim 13

The word-line driving circuit of claim 10 , wherein the third means supplies a chip erase signal to the second switching elements.

Claim 14

The word-line driving circuit of claim 10 , the non-volatile semiconductor memory also being operable in a second erase mode to erase the data in the memory cells coupled to a selectable block of the word lines, wherein, in the second erase mode, the third means supplies the mitigating potential to the second switching elements coupled to the word lines in the selectable block.

Claim 15

The word-line driving circuit of claim 12 , wherein the third means comprises: a first logic circuit receiving a chip erase signal and a block erase signal and generating a combined erase signal; and a plurality of second logic circuits providing the combined erase signal to the second switching elements under control of the first means.

Claim 16

A word-line driving circuit for a non-volatile semiconductor memory, the non-volatile semiconductor memory having a plurality of word lines and a plurality of memory cells coupled to the word lines, receiving first address signals and second address signals for selecting the word lines, and being operable in a write mode to store data in the memory cells, a read mode to read the stored data, and a first erase mode to simultaneously erase the stored data from the memory cells coupled to at least two of the word lines, the word-line driving circuit comprising: a plurality of first pre-decoders for decoding the first address signals, and supplying a writing potential in the write mode and an erasing potential in the first erase mode, responsive to the decoded first address signals; a plurality of second pre-decoders for decoding the second address signals and generating respective first selection signals; a plurality of third pre-decoders for decoding the first address signals generating respective second selection signals; a mitigating circuit for generating a third selection signal having a ground potential in the write mode and the read mode, and a mitigating potential intermediate between the ground potential and the erasing potential in the first erase mode; and a controller for generating a mode signal distinguishing the read mode from the write mode and the first erase mode; the word-line driving circuit also comprising, for each word line among the plurality of word lines, a first output means having a first node, a first switching element, and a second switching element, the first switching element and the second switching element being switched on and off by one of the first selection signals, the first switching element supplying the writing potential and the erasing potential from one of the first pre-decoders to the first node when switched on, the second switching element supplying the output signal from the mitigating circuit to the first node when switched on; a second output means having a second node, for supplying a reading potential to the second node responsive to one of the first selection signals and one of the second selection signals; and switching means for coupling said word line to said first node when the mode signal indicates the write mode or the first erase mode, and coupling said word line to the second node when the mode signal indicates the read mode.

Claim 17

A word-line driving circuit for a non-volatile semiconductor memory, the non-volatile semiconductor memory having a plurality of word lines and a plurality of memory cells coupled to the word lines, receiving first address signals and second address signals for selecting the word lines, and being operable in a write mode to store data in the memory cells, a read mode to read the stored data, and a first erase mode to simultaneously erase the stored data from the memory cells coupled to at least two of the word lines, the word-line driving circuit comprising: a plurality of first pre-decoders for decoding the first address signals, and supplying a writing potential in the write mode and an erasing potential in the first erase mode, responsive to the decoded first address signals; a plurality of second pre-decoders for decoding the second address signals and generating respective first selection signals; a plurality of third pre-decoders for decoding the first address signals generating respective second selection signals; a mitigating circuit for generating a third selection signal having a ground potential in the write mode and the read mode, and a mitigating potential intermediate between the ground potential and the erasing potential in the first erase mode; and a controller for generating a mode signal distinguishing the read mode from the write mode and the first erase mode; the word-line driving circuit also comprising, for each word line among the plurality of word lines, a first output means having a first node, a first switching element, and a second switching element, the first switching element and the second switching element being switched on and off by one of the first selection signals, the first switching element supplying the writing potential and the erasing potential from one of the first pre-decoders to the first node when switched on, the second switching element supplying the output signal from the mitigating circuit to the first node when switched on; a second output means having a second node, for supplying a reading potential to the second node responsive to one of the first selection signals and one of the second selection signals; and switching means for coupling said word line to said first node when the mode signal indicates the write mode or the first erase mode, and coupling said word line to the second node when the mode signal indicates the read mode.

Claim 18

The word-line driving circuit of claim 14 , wherein, in the first erase mode, the first decoders switch on all of the first switching elements, thereby driving all of the word lines to the erasing potential.

Claim 19

The word-line driving circuit of claim 15 , wherein the third selection signal is a chip erase signal.

Claim 20

The word-line driving circuit of claim 15 , the non-volatile semiconductor memory also being operable in a second erase mode to erase the stored data from the memory cells coupled to a selectable block of the word lines, wherein the mitigating circuit comprises: a first logic circuit receiving a chip erase signal and a block erase signal and generating a combined erase signal; and a plurality of second logic circuits generating the third selection signal for respective second switching elements from the combined erase signal under control of the second decoders.