US6704224B2
Expired / Lapsed
US
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Non-volatile semiconductor memory apparatus
Assignee: Seiko Epson Corp
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Filing: 2002-09-19
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Granted: 2004-03-09
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Expires: 2022-09-19
Abstract
Abstract The invention achieves a high speed access when shifting to an active mode from a standby mode, in particular immediately after shifting to a read, and reduces the current consumption at the time of standby. A strong charge pump generates 5.0V and a power supply voltage of 8.0V. The power supply voltage is supplied to constant voltage circuits. The constant voltage circuits generate voltages VPBL, VPYS, VPCGL, VPCGL, VPCGH and VPCGH, respectively, according to the respective read, program and erase operation modes. The constant voltage circuit that operates in active modes consumes a large amount of current when it supplies the voltage VPCGH. In contrast, the constant voltage circuit operates with a low current consumption and generates the voltage VPCGH in the standby mode. With the voltage VPCGH that is generated by the constant voltage circuit in the standby mode, a high speed access is possible when shifting from the standby mode to the active mode, and in particular, immediately after shifting to a read mode. Also, the current consumption in the standby mode can be substantially reduced.
Inventors
- 👤 Kanji Natori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C5/00; G11C5/14; G11C5/145; G11C7/00; G11C7/22; G11C16/04; G11C16/0466; G11C16/0475; G11C2207/00; G11C2207/22; G11C2207/2227
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
125 words
A non-volatile semiconductor memory apparatus, comprising: a charge pump device that steps up and outputs a power supply voltage; a memory array formed of a plurality of non-volatile memory elements; an operation voltage setting device that sets operation voltages to execute plural modes for a specified non-volatile memory element of the plurality of non-volatile memory elements; a constant voltage device for activation that is provided with voltages output from the charge pump device to generate the operation voltages in an active state; and a constant voltage device for standby that is provided with a voltage output from the charge pump device to generate a voltage based on the operation voltage with a lower current consumption than voltages generated by the constant voltage device for activation.
Claim 2
Dependent Claim
125 words
A non-volatile semiconductor memory apparatus, comprising: a charge pump device that steps up and outputs a power supply voltage; a memory array formed of a plurality of non-volatile memory elements; an operation voltage setting device that sets operation voltages to execute plural modes for a specified non-volatile memory element of the plurality of non-volatile memory elements; a constant voltage device for activation that is provided with voltages output from the charge pump device to generate the operation voltages in an active state; and a constant voltage device for standby that is provided with a voltage output from the charge pump device to generate a voltage based on the operation voltage with a lower current consumption than voltages generated by the constant voltage device for activation.
Claim 3
Dependent Claim
30 words
The non-volatile semiconductor memory apparatus according to claim 1 , the operation voltage generated by the constant voltage device for standby being a voltage higher than the power supply voltage.
Claim 4
Dependent Claim
29 words
The non-volatile semiconductor memory apparatus according to claim 1 , the constant voltage device for standby generating an operation voltage for a read mode for the non-volatile memory element.
Claim 5
Dependent Claim
26 words
The non-volatile semiconductor memory apparatus according to claim 1 , the charge pump device stepping up the power supply voltage to generate a plurality of voltages.
Claim 6
Dependent Claim
36 words
The non-volatile semiconductor memory apparatus according to claim 1 , the constant voltage device being capable of generating constant voltages of different voltage values depending on read, program or erase mode for the non-volatile memory element.
Claim 7
Dependent Claim
35 words
The non-volatile semiconductor memory apparatus according to claim 1 , the non-volatile memory element being a memory element that forms a twin memory cell controlled by one word gate and first and second control gates.
Claim 8
Dependent Claim
45 words
The non-volatile semiconductor memory apparatus according to claim 6 , the operation voltage setting device setting voltage values provided from the constant voltage devices independently for the first and second control gates, and an impurity layer to access trapped charge of the non-volatile memory element.
Claim 9
Dependent Claim
129 words
The non-volatile semiconductor memory apparatus according to claim 6 , the operation voltage setting device including: a word line connected to a word gate of the twin memory cell in the same row; a control gate line that is commonly connected to the mutually adjacent first and second control gates in the same column of the twin memory cells arranged adjacent to each other in a row direction; and a bit line that is commonly connected to impurity layers to access trapped charge arranged in the same column of the mutually adjacent non-volatile memory elements of the twin memory cells arranged adjacent to each other in the row direction, voltage values provided from the constant voltage devices being set independently for the control gate line and the bit line.
Claim 10
Dependent Claim
38 words
The non-volatile semiconductor memory apparatus according to claim 1 , the non-volatile memory element including an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O) as a charge trap site.
Claim 11
Dependent Claim
174 words
A non-volatile semiconductor memory apparatus, comprising: a charge pump device that steps up and outputs a power supply voltage; a memory array formed of a plurality of twin memory cells that each have two non-volatile memory elements; an operation voltage setting device that sets an operation voltage to execute each of reading, programming and erasing operations for a specified non-volatile memory element of the plurality of twin memory cells that each have two non-volatile memory elements controlled by one word gate, and first and second control gates; a constant voltage device for activation that is provided with voltages output from the charge pump device to generate the operation voltages in an active mode; and a constant voltage device for standby that is provided with a voltage output from the charge pump device to generate in an active mode a voltage based on the operation voltage to be supplied to the first and second control gates in a read mode with a lower current consumption than voltages generated by the constant voltage device for activation.
Claim 12
Dependent Claim
174 words
A non-volatile semiconductor memory apparatus, comprising: a charge pump device that steps up and outputs a power supply voltage; a memory array formed of a plurality of twin memory cells that each have two non-volatile memory elements; an operation voltage setting device that sets an operation voltage to execute each of reading, programming and erasing operations for a specified non-volatile memory element of the plurality of twin memory cells that each have two non-volatile memory elements controlled by one word gate, and first and second control gates; a constant voltage device for activation that is provided with voltages output from the charge pump device to generate the operation voltages in an active mode; and a constant voltage device for standby that is provided with a voltage output from the charge pump device to generate in an active mode a voltage based on the operation voltage to be supplied to the first and second control gates in a read mode with a lower current consumption than voltages generated by the constant voltage device for activation.
References Cited (Backward Citations)
JPH07161851A
Cited
US5408115A
Cited
US5422504A
Cited
US5494838A
Cited
US5969383A
Cited
US5986935A
Cited
JP2978477B1
Cited
JP2001156188A
Cited
US6255166B1
Cited
US6177318B1
Cited
US6248633B1
Cited
US6584032B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-03-09 | 2007-09-08 | 2008-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-03-09 | 2011-09-08 | 2012-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-03-09 | 2015-09-08 | 2016-03-09 | $7700.00 | Window Closed / Lapsed |