A data processor comprising look aside buffer and method therefor

Claim 2

The data processor of claim 1 wherein the first validity bit selectively disables each of the first portion of the plurality of memory cells from comparing the bit stored therein with the predetermined bit of the logical address value.

Claim 3

The data processor of claim 1 wherein the memory further comprises: a second validity bit (130) which is coupled to the interface means for storing a second control value and which is coupled between the second portion of the plurality of memory cells and a third portion of the plurality of memory cells, the second validity bit selectively enabling each of the second portions of the plurality of memory cells to compare the bit stored therein with the predetermined bit of the logical address value.

Claim 4

A data processor (10), comprising: interface means (24)for communicating a plurality of logical address values and a plurality of control values; and a memory coupled to the interface means for receiving the logical address values and the control values, the memory comprising; a plurality of memory cells (126) coupled to the interface means for receiving the logical address values wherein each of the plurality of memory cells is composed of a plurality of memory cell bits which store a bit of a stored address value and each bit capable of selectively comparing a bit of the stored address value to a predetermined bit of the logical address value; and a plurality of validity bits (128, 130, 132) which are coupled to the interface means for storing a plurality of the control values and which are coupled at least one memory cell, and the validity bits are capable of selectively enabling each memory cell bit in a memory cell with which it is coupled.

Claim 5

The data processor of claim 1 wherein the plurality of validity bits selectively disable the memory cell bits in the memory cells with which they are coupled.

Claim 6

A lookaside buffer (70) which comprises: interface means (52, 40) for communicating a logical address value and control values; and a CAM array (120)coupled with the interface means comprising a plurality of CAM cell rows (121); at least two CAM cells per row composed of a plurality of CAM cell bits (126) which can store a possible address value and compare it to a logical address value; a conductive line for each row connected to each CAM cell bit in the row; a plurality of validity bits (128) coupled to the CAM cells and interface means on at least one side and connected to the conductive line wherein the validity bits are capable of selectively isolating the CAM cells on at least a first side of the CAM cell bits on a second side; a RAM array (122) coupled to the conductive line for each row of the CAM array comprising a plurality of RAM cell bits for storing a translated address; and multiplexing means (100) connected to the interface means and the RAM array for multiplexing the logical address with the control values and the translated addresses to generate a physical address.