Patent US4556943A successfully refreshed from Google Patents.
Patent US3875207A successfully refreshed from Google Patents.
Patent US1965836A successfully refreshed from Google Patents.
Patent JPS5659596A successfully refreshed from Google Patents.
Patent US4633439A successfully refreshed from Google Patents.
US4633439A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Superconducting read-only memories or programable logic arrays having the same
Assignee: Hitachi Ltd
•
Filing: 1983-07-20
•
Granted: 1986-12-30
•
Expires: 2003-07-20
Abstract
Abstract An A.C. powered type logic array of very high speed operations which employs Josephson devices and which can program any desired logic. The logic array comprises a first logic array which delivers AND logic signals of desired ones of input signals, and a second logic array which delivers OR logic signals of desired ones of the AND outputs. Each of the first and second logic arrays comprises a plurality of bit lines which connect a plurality of arrayed Josephson devices in series at respective rows and each of which has one end connected to a power source and the other end grounded through a resistor, and word lines which are arranged in the column direction of the Josephson device array and which are selectively coupled to the Josephson devices. Whether or not the word lines are coupled to the respective Josephson devices of the arrays, is determined by the patterns of the word lines or the patterns of the Josephson devices, thereby to program the desired logic.
Inventors
- 👤 Yutaka Harada
- 👤 Toshikazu Nishino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:38
CPC Classifications
H; H10; H10N; H10N69/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/44; H03; H03K; H03K19/00; H03K19/02; H03K19/195; H03K19/1952; H03K3/00; H03K3/02; H03K3/38; Y; Y10; Y10S; Y10S505/00; Y10S505/825; Y10S505/831; Y10S505/832
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
353 words
A superconducting programable logic array comprising: (a) first bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each first bit line being connected to an ac voltage source having a predetermined phase and a second terminal thereof being grounded; (b) first Josephson junctions respectively connecting two neighboring line portions of said plurality of first bit lines and respectively having predetermined programed states; (c) first word lines arranged to cross said first bit lines and each connected to one of said Josephson junctions belonging to each of said first bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied input signal; (d) second bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each second bit line being connected to an ac voltage source having said predetermined phase and a second terminal thereof being grounded; (e) second Josephson junctions respectively connecting two neighboring line portions of said plurality of second bit lines, and respectively having predetermined programed states; (f) second word lines each provided in correspondence to one of said first bit lines, arranged to cross said second bit lines and each connected to one of said Josephson junctions belonging to each of said second bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied control signal; (g) a plurality of gate means connected to said first bit lines, said second word lines and an ac voltage source having said predetermined phase, said gate means including means for inverting signals from respective first bit lines and for supplying the inverted signals to second word lines which respectively correspond to said first bit lines as a control signal in response to a timing signal applied to said gate means which is out of phase with the predetermined phase; and (h) output means connected to said second bit lines for deriving signals corresponding to predetermined programable states of said second Josephson junctions from said second bit lines.
Claim 2
Dependent Claim
353 words
A superconducting programable logic array comprising: (a) first bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each first bit line being connected to an ac voltage source having a predetermined phase and a second terminal thereof being grounded; (b) first Josephson junctions respectively connecting two neighboring line portions of said plurality of first bit lines and respectively having predetermined programed states; (c) first word lines arranged to cross said first bit lines and each connected to one of said Josephson junctions belonging to each of said first bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied input signal; (d) second bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each second bit line being connected to an ac voltage source having said predetermined phase and a second terminal thereof being grounded; (e) second Josephson junctions respectively connecting two neighboring line portions of said plurality of second bit lines, and respectively having predetermined programed states; (f) second word lines each provided in correspondence to one of said first bit lines, arranged to cross said second bit lines and each connected to one of said Josephson junctions belonging to each of said second bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied control signal; (g) a plurality of gate means connected to said first bit lines, said second word lines and an ac voltage source having said predetermined phase, said gate means including means for inverting signals from respective first bit lines and for supplying the inverted signals to second word lines which respectively correspond to said first bit lines as a control signal in response to a timing signal applied to said gate means which is out of phase with the predetermined phase; and (h) output means connected to said second bit lines for deriving signals corresponding to predetermined programable states of said second Josephson junctions from said second bit lines.
Claim 3
Dependent Claim
29 words
A superconducting programable logic array according to claim 1, wherein said first bit lines are perpendicular to said second bit lines and are parallel to said second word lines.
Claim 4
Dependent Claim
16 words
A superconducting programable logic array according to claim 1, wherein said inverted signals are ac signals.
Claim 5
Dependent Claim
99 words
A superconducting programable logic array according to claim 3, wherein said plurality of gate means each comprises a first Josephson OR circuit controlled by a signal from a corresponding one of said first bit lines and connected to an ac voltage source having said predetermined phase, a second Josephson OR circuit controlled by the applied timing signal and connected to the first Josephson OR circuit and a current injection type Josephson AND circuit connected to said second Josephson OR circuit and an ac voltage source having said predetermined phase for providing the inverted signal to said second word line.
Claim 6
Dependent Claim
308 words
A superconducting programable logic array comprising: (a) first bit lines arranged in parallel to one another including a plurality of line portions, said first bit lines each being connected to an ac voltage source having a predetermined phase; (b) first Josephson junctions respectively connecting two neighboring line portions of said plurality of first bit lines and respectively having predetermined programed states; (c) first word lines arranged to cross said first bit lines and each connected to one of said Josephson junctions belonging to each of said first bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied input signal; (d) second bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each second bit line being connected to an ac voltage source having said predetermined phase and a second terminal thereof being grounded; (e) second Josephson junctions respectively connecting two neighboring line portions of said plurality of second bit lines, and respectively having predetermined programed states; (f) second word lines each provided in correspondence to one of said first bit lines, arranged to cross said second bit lines and each connected to one of said Josephson junctions belonging to each of said second bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied control signal; (g) a plurality of gate means connected to said first bit lines and said second word lines for supplying control signals from said first bit lines to corresponding second word lines in response to an applied timing signal which is out of phase with the predetermined phase; and (h) output means connected to said second bit lines for deriving signals corresponding to predetermined programable states of said second Josephson junctions from said second bit lines.
Claim 7
Dependent Claim
308 words
A superconducting programable logic array comprising: (a) first bit lines arranged in parallel to one another including a plurality of line portions, said first bit lines each being connected to an ac voltage source having a predetermined phase; (b) first Josephson junctions respectively connecting two neighboring line portions of said plurality of first bit lines and respectively having predetermined programed states; (c) first word lines arranged to cross said first bit lines and each connected to one of said Josephson junctions belonging to each of said first bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied input signal; (d) second bit lines arranged in parallel to one another and each including a plurality of line portions, a first terminal of each second bit line being connected to an ac voltage source having said predetermined phase and a second terminal thereof being grounded; (e) second Josephson junctions respectively connecting two neighboring line portions of said plurality of second bit lines, and respectively having predetermined programed states; (f) second word lines each provided in correspondence to one of said first bit lines, arranged to cross said second bit lines and each connected to one of said Josephson junctions belonging to each of said second bit lines for controlling electric states of the Josephson junctions it is connected to in response to an applied control signal; (g) a plurality of gate means connected to said first bit lines and said second word lines for supplying control signals from said first bit lines to corresponding second word lines in response to an applied timing signal which is out of phase with the predetermined phase; and (h) output means connected to said second bit lines for deriving signals corresponding to predetermined programable states of said second Josephson junctions from said second bit lines.
Claim 8
Dependent Claim
29 words
A superconducting programable logic array according to clam 5, wherein said first bit lines are perpendicular to said second bit lines and are parallel to said second word lines.
Claim 9
Dependent Claim
29 words
A superconducting programable logic array according to clam 5, wherein said first bit lines are perpendicular to said second bit lines and are parallel to said second word lines.
Claim 10
Dependent Claim
21 words
A superconducting programable logic array according to claim 5, wherein said supplied signals to said second word lines are ac signals.
Claim 11
Dependent Claim
58 words
A superconducting programable logic array according to claim 7, wherein said plurality of gate means each comprises a current injection type Josephson AND circuit for providing control signals to one of said second word lines in accordance with a signal supplied from a corresponding one of said first bit lines when the timing signal exceeds a predetermined threshold.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |