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US4809224A Expired / Lapsed US ⏱️ 0.0 years remaining

Read only memory device with memory cells each storing one of three states

Assignee: Fujitsu Ltd
•
Filing: 1987-08-07
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Granted: 1989-02-28
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Expires: 2007-08-07
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Abstract

Abstract A ROM device includes a plurality of memory cells each storing one of three states, a cell voltage generating circuit for providing a cell voltage corresponding to the state stored in a selected one of the memory cells, and a reference cell for providing a reference voltage which is substantially the same as the cell voltage provided by a memory cell storing an intermediate state of the three states. The ROM also includes a comparator circuit for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage.

Inventors

  • 👤 Yasuo Suzuki
  • 👤 Yasuaki Suzuki
  • 👤 Hiroshi Hirao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 13:13
CPC Classifications
G; G11; G11C; G11C17/00; G11C11/00; G11C11/56; G11C11/5692

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 122 words
A read only memory device comprising: a plurality of memory cells each storing one of three states; a cell voltage generating circuit connected to said plurality of memory cells for providing a cell voltage corresponding to the state stored in a selected one of said plurality of memory cells; a reference cell provided for said plurality of memory cells for providing a reference voltage which is substantially the same as the cell voltage provided by a memory cell storing an intermediate state of the three states; and a comparator circuit connected to said cell voltage generating circuit and said reference cell for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage.
Claim 2
Dependent Claim 122 words
A read only memory device comprising: a plurality of memory cells each storing one of three states; a cell voltage generating circuit connected to said plurality of memory cells for providing a cell voltage corresponding to the state stored in a selected one of said plurality of memory cells; a reference cell provided for said plurality of memory cells for providing a reference voltage which is substantially the same as the cell voltage provided by a memory cell storing an intermediate state of the three states; and a comparator circuit connected to said cell voltage generating circuit and said reference cell for generating a logical output signal based on the result of a comparison between the cell voltage and the reference voltage.
Claim 3
Dependent Claim 39 words
A read only memory device according to claim 1, wherein said memory cells comprise memory cell transistors, and said three states of said memory cells transistors are realized by changing the effective gate width of said memory cell transistors.
Claim 4
Dependent Claim 68 words
A read only memory according to claim 1, wherein said comparator circuit comprises: a first load transistor and a second load transistor each connected to a voltage source; a first switching transistor connected between said first load transistor and said cell level voltage generating circuit and controlled by said reference voltage; and a second switching transistor connected to said second load transistor and controlled by the cell voltage.
Claim 5
Dependent Claim 42 words
A read only memory according to claim 1, further comprising a decoding circuit connected to said cell level voltage generator circuit, said reference cell, and said comparator circuit for producing decoder output signals corresponding to three states stored in said memory cells.
Claim 6
Dependent Claim 24 words
A memory cell according to claim 4, wherein said decoding circuit is constituted by a combination of differential amplifiers, inverters, and a NOR gate.

References Cited (Backward Citations)

US32401A Cited
USRE32401E Cited
US4503518A Cited
US4404655A Cited
US4449203A Cited
US4653023A Cited
JPS61183329A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-28 1992-08-29 1993-02-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-28 1996-08-29 1997-02-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-28 2000-08-29 2001-02-28 $7700.00 Window Closed / Lapsed

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