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US4994402A
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Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1989-08-30
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Granted: 1991-02-19
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Expires: 2009-08-30
Abstract
Abstract A method of fabricating a coplanar, self-aligned contact structure in a semiconductor device. Polysilicon pads are placed on top of field oxide regions which adjoin source and drain diffusion regions of the device. Strips of highly conductive material such as titanium silicide or titanium nitride are formed on top of each pad; each strip extends down a side of its pad to an adjoining diffusion region, thereby establishing a conductive path between the diffusion region and the top of the pad. Contacts are established by etching holes through a passivation layer which covers the device to reach the conductive strips on top of the pads.
Inventors
- 👤 Kuang-Yi Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:38
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10W20/069; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441; H10D30/0212; Y; Y10; Y10S; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
201 words
A method of forming a coplanar self-aligned contact structure in a semiconductor device, the method comprising: forming first and second field oxide regions in a planar surface of a substrate, the regions being separated from each other by an island region of the substrate; forming a gate oxide layer in the planar surface of the island region; forming three coplanar polysilicon pads, a first such pad overlying the first field oxide region, a second such pad overlying the second field oxide region and a third such pad overlying the gate oxide layer to define a gate region; forming in the island region a source diffusion region between the gate region and the first field oxide region and a drain diffusion region between the gate region and the second field oxide region; coating the pads and the substrate with a refractive metal; coating the metal with a reactive layer; forming first and second conductors from the metal and the reactive layer, the first and second conductors being in electrical contact with the source and drain regions, respectively, and extending therefrom to and over the first and second pads; and establishing electrical contacts with the portions of the conductors which cover the pads.
Claim 2
Independent Claim
201 words
A method of forming a coplanar self-aligned contact structure in a semiconductor device, the method comprising: forming first and second field oxide regions in a planar surface of a substrate, the regions being separated from each other by an island region of the substrate; forming a gate oxide layer in the planar surface of the island region; forming three coplanar polysilicon pads, a first such pad overlying the first field oxide region, a second such pad overlying the second field oxide region and a third such pad overlying the gate oxide layer to define a gate region; forming in the island region a source diffusion region between the gate region and the first field oxide region and a drain diffusion region between the gate region and the second field oxide region; coating the pads and the substrate with a refractive metal; coating the metal with a reactive layer; forming first and second conductors from the metal and the reactive layer, the first and second conductors being in electrical contact with the source and drain regions, respectively, and extending therefrom to and over the first and second pads; and establishing electrical contacts with the portions of the conductors which cover the pads.
Claim 3
Dependent Claim
65 words
A method according to claim 1 wherein the step of forming the conductors comprises: etching the reactive layer to form a first strip overlying the first pad and extending therefrom to and over a portion of the source region and a second strip overlying the second pad and extending therefrom to and over a portion of the drain region; and annealing to form the conductors.
Claim 4
Dependent Claim
13 words
A method according to claim 2 wherein the reactive layer comprises amorphous silicon.
Claim 5
Dependent Claim
77 words
A method according to claim 3 wherein the annealing step comprises: annealing at a relatively low temperature to react that portion of the metal which is covered by the amorphous silicon strips with the amorphous silicon and to react that portion of the metal which covers the source and drain regions of the substrate and which is not covered by the amorphous silicon with the substrate; removing any unreacted metal; and annealing at a relatively high temperature.
Claim 6
Dependent Claim
87 words
A method according to claim 1 wherein the step of forming the conductors comprises: annealing at a relatively low temperature to form a nitride over oxide portions of the device and a silicon compound over silicon portions; etching to form a first conducting strip overlying the first pad and extending therefrom to and over a portion of the source region and a second strip overlying the second pad and extending therefrom to and over a portion of the drain region; and annealing at a relatively high temperature.
Claim 7
Dependent Claim
19 words
A method according to claim 5 wherein the refractory metal comprises titanium and the reactive layer comprises titanium nitride.
Claim 8
Dependent Claim
48 words
A method according to claim 1 wherein the step of forming the diffusion regions comprises: coating the pads and the substrate with a dielectric layer; directionally etching the dielectric layer to provide oxide spacers around the pads; and performing ion implantation and drive-in to form the diffusion regions.
Claim 9
Dependent Claim
44 words
A method according to claim 1 wherein the step of forming the three pads comprises forming a polysilicon layer over the island region and a portion of each of the field oxide regions and etching the polysilicon layer and the underlying gate oxide layer.
Claim 10
Dependent Claim
79 words
A method according to claim 1 wherein the step of establishing electrical contacts comprises: forming a passivation layer over the conductors; making a first hole through the passivation layer over the first pad to the first conductor and a second hole through the passivation layer over the second pad to the second conductor, the holes being of similar depth; and depositing metal in each hole to establish an electrical contact with the conductor at the bottom of the hole.
Claim 11
Dependent Claim
108 words
A method according to claim 1 wherein the step of establishing electrical contacts comprises: covering the semiconductor, except the portions of the conductors which overlie the pads, with a first dielectric layer; covering the first layer and the exposed portions of the conductors with a second dielectric layer; making a first hole through the second dielectric layer over the first pad to the first conductor and a second hole through the second dielectric layer over the second pad to the second conductor, the holes being of similar depth; and depositing metal in each hole to establish an electrical contact with the conductor at the bottom of the hole.
Claim 12
Dependent Claim
59 words
A method according to claim 10 wherein the step of covering the semiconductor with the first dielectric layer comprises covering the entire semiconductor with the first delectric layer, spinning a thick photoresist over the first dielectric layer, and etching back to planarize the dielectric layer down to the level of the portions of the conductors which overly the pads.
Claim 13
Dependent Claim
37 words
A method according to claim 10 wherein the step of making the holes comprises etching with an etchant that acts at least ten times more rapidly on the second dielectric layer than on the first dielectric layer.
Claim 14
Dependent Claim
20 words
A method according to claim 10 wherein one of the holes is wider than the pad which is beneath it.
References Cited (Backward Citations)
JPS5329088A
Cited
US4208781A
Cited
JPS53105989A
Cited
US4384399A
Cited
US4333225A
Cited
GB2062959A
Cited
JPS574141A
Cited
US4402126A
Cited
US4462149A
Cited
WO1983002197A1
Cited
US4443930A
Cited
US4826786A
Cited
JPS62128546A
Cited
US4767724A
Cited
US4788160A
Cited
US4822749A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |