Non-volatile memory with hot carriers transmitted to floating gate through control gate

Claim 2

A non-volatile semiconductor memory device comprising: means for injecting a first type of charges, said means for injecting a first type of charges comprising: a first charge injecting electrode; a first insulating film formed on said charge injecting electrode for passing a tunnel current; a first control electrode formed on said first insulating film, wherein said first charge injecting electrode, said first insulating film and said first control electrode are formed overlapping at least in a first overlap region; a second insulating film formed on said first control electrode; and a floating electrode formed on said second insulating film; means for sensing an amount of total charges stored in said floating electrode, wherein said second insulating film and said electrode are formed overlapping at least on said first overlap region, and wherein said first charge injecting electrode is connected to a high potential and said first charge injecting electrode emits said first type of charges, and said first type of charges is stored in said floating electrode, said first type of charges is injected into and stored in said floating electrode through said first insulating film, said first control electrode and said second insulating film.

Claim 3

A non-volatile semiconductor memory according to claim 1, wherein said first control electrode is a thin conductive film having a thickness of less than approximately 100 angstroms.

Claim 4

A non-volatile semiconductor memory device according to claim 1, wherein said first type of charges are electrons, and said first charge injecting electrode comprises an n type semiconductor.

Claim 5

A non-volatile semiconductor memory device according to claim 1, wherein said first type of charges are holes, and said charge injecting electrode comprises a p type semiconductor.

Claim 6

A non-volatile semiconductor memory device according to claim 1 further comprising: a third insulating film formed on said floating electrode; an auxiliary control electrode formed on said third insulating film such that said auxiliary control is capacitively coupled to said floating electrode.

Claim 7

A non-volatile semiconductor memory device according to claim 1 further comprising: means for injecting a second type of charges, said means for injecting a second type of charges comprising: a second charge injecting electrode; a fourth insulating film formed on said second charge injecting electrode for passing tunnel current; a second control electrode formed on said fourth insulating film; wherein said second charge injecting electrode, said fourth insulating film, and said second control electrode are formed overlapping at least in a second overlap region, and wherein said means for injecting a second type of charges is set such that said second control electrode is in contact with said second insulating film, and said means for injecting a second type of charges is also set on the same side of said second insulating film as said means for injecting a first type of charges, and said means for injecting a second type of charges is also set such that said second insulating film and said floating gate are formed overlapping at least in said second overlap region; and wherein said second charge injecting electrode is connected to a high potential and said second charge injecting electrode emits said second type of charges, said second type of charges is stored in said floating electrode, said second type of charges is injected into and stored in said floating electrode through said fourth insulating film, said second control electrode and said second insulating film.

Claim 8

A non-volatile semiconductor memory device according to claim 6 wherein: said third insulating film is formed on said floating electrode; said auxiliary control electrode is formed on said third insulating film such that said auxiliary control electrode is capacatively coupled to said floating electrode.

Claim 9

A non-volatile semiconductor memory device according to claim 1, wherein said first type of charges are electrons and said means for injecting said first type of charges further comprises: a first charge injecting electrode having a p++ type semiconductor; a first control electrode having an n++ type semiconductor; wherein said first charge injecting electrode and said first control electrode are formed overlapping at least in a first overlap region, and wherein a reverse voltage is applied between said p++ type semiconductor and said n++ type semiconductor such that an energy gap at a p-n junction is used as an energy barrier for passing a tunneling current.

Claim 10

A non-volatile semiconductor memory device according to claim 1, wherein said first type of charges are electrons and said means for injecting said first type of charges further comprises: a first charge injecting electrode having an n++ type semiconductor; a first control electrode having a p++ type semiconductor; wherein said first charge injecting electrode and said first control electrode are formed overlapping at least in a first overlap region, and wherein a reverse voltage is applied between said n++ type semiconductor and said p++ type semiconductor such that an energy gap at a p-n junction is used as an energy barrier for passing a tunnel current.

Claim 11

A non-volatile semiconductor memory device according to claim 8, wherein said first control electrode has a thickness of less than approximately 100 angstroms.

Claim 12

A non-volatile semiconductor memory device according to claim 9, wherein said first control electrode has a thickness of less than approximately 100 angstroms.

Claim 13

A non-volatile semiconductor memory device according to claim 8 wherein: said third insulating film is formed on said floating electrode; said auxiliary control electrode is formed on said third insulating film such that said auxiliary control electrode is capacitively coupled to said floating electrode.

Claim 14

A non-volatile semiconductor memory device according to claim 9 wherein: said third insulating film is formed on said floating electrode; said auxiliary control electrode is formed on said third insulating film such that said auxiliary control electrode is capacitively coupled to said floating electrode.

Claim 15

A non-volatile semiconductor memory device according to claim 8 further comprising: means for injecting holes, said means for injecting holes further including: a second charge injecting electrode having an n++ type semiconductor; a second control electrode having a p++ type semiconductor; wherein said second charge injecting electrode and said second control electrode are formed overlapping at least in a second overlap region, and wherein said means for injecting holes is set such that said second control electrode is in contact with said second insulating film, and said means for injecting holes is set on the same side of said second insulating film as said means for injecting said first type of charges, and said means for injecting holes is set such that said second insulating film and said floating gate are formed overlapping at least in said second overlap region.

Claim 16

A non-volatile semiconductor memory device according to claim 14 wherein: said third insulating film is formed on said floating electrode; said auxiliary control electrode is formed on said third insulating film such that said auxiliary control electrode is capacitively coupled to said floating device.