Single transistor EEPROM architecture

Claim 2

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being directly connected to the bit line, and the second current terminal of the last memory cell in the string being connected to the reference voltage point; and a decoder having a plurality of outputs respectively connected to the control terminals of the memory cells and operatively responsive to a memory address during a conduction threshold set mode for applying a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising any of the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a third voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell.

Claim 3

A memory as in claim 1, wherein the conduction threshold is a high voltage threshold, and the first voltage is positive relative to the bit line voltage.

Claim 4

A memory as in claim 1, wherein the conduction threshold is a low voltage threshold, and the first voltage is negative relative to the bit line voltage.

Claim 5

A memory as in claim 1, wherein the decoder further is operatively responsive to a memory address during a read mode for applying a third voltage to the control terminal of at least a second addressed one of the memory cells in the string and a fourth voltage to the control terminals of a second subset of memory cells comprising the memory cells in the string intervening between the second addressed memory cell and the bit line, and between the second addressed memory cell and the reference voltage point, the fourth voltage being such as to support conduction in the memory cells of the second subset, and the third voltage being such as to support sensing the conduction threshold in the second addressed memory cell.

Claim 6

A memory as in claim 3 wherein: the memory cells are field effect devices fabricated in a semiconductor substrate, each having a control gate coupled to the control terminals, a floating gate, and a channel region in the substrate between a source and a drain, under electrostatic control of the control gate and the floating gate; and wherein a substrate potential is applied to the substrate.

Claim 7

A memory as in claim 5 wherein the substrate potential is a ground potential.

Claim 8

A memory as in claim 5, wherein the substrate potential is variable so that the absolute values of the first and third voltages relative to ground potential are less that the absolute value of the difference between the first and third voltages.

Claim 9

A memory as in claim 1 wherein each of the memory cells is an n-type electrically erasable programmable read only memory ("EEPROM") device implemented on a semiconductor substrate, the control terminal being a control gate, the first current terminal being a drain, and the second current terminal being a source.

Claim 10

A memory as in claim 8 wherein within the string, adjacent EEPROM devices are connected source-to-source and drain-to-drain, alternately.

Claim 11

A memory as in claim 8 wherein within the string, adjacent EEPROM devices are connected source-to-drain, the drain of the first memory cell in the string being directly connected to the bit line, and the source of the last memory cell in the string being connected to the reference voltage point.

Claim 12

A memory as in claim 8 wherein the decoder is operable in a erase mode: to apply a fourth voltage to the voltage reference point and a fifth voltage to the substrate; to set the second voltage positive to the fifth voltage and of a magnitude so that conduction is supported in an EEPROM device without causing tunneling therein; and to bring the first voltage positive to the third voltage and of a magnitude so that tunneling is supported in an EEPROM device.

Claim 13

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being directly connected to the bit line, and the second current terminal of the last memory cell in the string being directly connected to the reference voltage point; and a decoder having a plurality of outputs respectively connected to the control terminals of the memory cells and operatively responsive to a memory address during a conduction threshold set mode for applying a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell.

Claim 14

A programmable erasable memory comprising: a bit line; a reference voltage point; a plurality of memory cells, each having first and second current terminals and a control terminal for controlling current through the first and second current terminals, and further having a conduction threshold settable in accordance with a first potential difference across the control terminal and the first current terminal thereof, the memory cells being serially connected by the first and second current terminals thereof to form a string having at least a first memory cell and a last memory cell, the first current terminal of the first memory cell in the string being directly connected to the bit line, and the second current terminal of the last memory cell in the string being directly connected to the reference voltage point; and a decoder having a plurality of outputs respectively connected to the control terminals of the memory cells and operatively responsive to a memory address during a conduction threshold set mode for applying a first voltage to the control terminal of at least a first addressed one of the memory cells in the string and a second voltage to the control terminals of a first subset of memory cells comprising the memory cells in the string intervening between the addressed memory cell and the bit line, the second voltage being such as to support conduction in the memory cells of the first subset, and the first voltage being such, relative to a voltage on the bit line, as to support setting the conduction threshold in the first addressed memory cell.

Claim 15

A programmable erasable integrated circuit memory comprising a plurality of bit lines, a plurality of reference voltage points, and a plurality of NAND structures arranged in an array, the NAND structures of a common row being connected to respective bit lines and sharing a common set of word lines and at least one common reference voltage point, and the NAND structures of a common column being connected to respective sets of word lines and sharing a respective one of the bit lines, each of the NAND structures comprising: a plurality of EEPROM devices serially connected by their respective sources and drains and having respective control gates connected to respective word lines of an associated one of the sets of word lines, each of the EEPROM devices having a floating gate overlapping a portion of the drain thereof, one of the source and drain nodes of a first one of the EEPROM devices in the series being unconnected to a neighboring EEPROM device and directly connected by a conductor to an associated one of the bit lines, and one of the source and drain nodes of a last one of the EEPROM devices in the series being unconnected to a neighboring EEPROM device and directly connected by a conductor to one of the reference voltage points; means for applying a substrate bias to the EEPROM devices; means for applying a first voltage to the associated bit line; and means for applying a second voltage to a selected one of the word lines of the associated set of word lines and a third voltage to nonselected ones of the word lines of the associated set of word lines, the third voltage being such relative to the substrate bias as to support conduction in the EEPROM devices, and the second voltage being such relative to the first voltage as to support Fowler-Nordheim tunneling between the drain and the floating gate of the EEPROM device having its control gate connected to the selected word line.

Claim 16

A programmable erasable integrated circuit memory comprising a plurality of bit lines, a plurality of reference voltage points, and a plurality of NAND structures arranged in an array, the NAND structures of a common row being connected to respective bit lines and sharing a common set of word lines and at least one common reference voltage point, and the NAND structures of a common column being connected to respective sets of word lines and sharing a respective one of the bit lines, each of the NAND structures comprising: a plurality of EEPROM devices serially connected by their respective sources and drains and having respective control gates connected to respective word lines of an associated one of the sets of word lines, each of the EEPROM devices having a floating gate overlapping a portion of the drain thereof, one of the source and drain nodes of a first one of the EEPROM devices in the series being unconnected to a neighboring EEPROM device and directly connected by a conductor to an associated one of the bit lines, and one of the source and drain nodes of a last one of the EEPROM devices in the series being unconnected to a neighboring EEPROM device and directly connected by a conductor to one of the reference voltage points; means for applying a substrate bias to the EEPROM devices; means for applying a first voltage to the associated bit line; and means for applying a second voltage to a selected one of the word lines of the associated set of word lines and a third voltage to nonselected ones of the word lines of the associated set of word lines, the third voltage being such relative to the substrate bias as to support conduction in the EEPROM devices, and the second voltage being such relative to the first voltage as to support Fowler-Nordheim tunneling between the drain and the floating gate of the EEPROM device having its control gate connected to the selected word line.

Claim 17

A memory as in claim 13 wherein the EEPROM devices are n-channel devices and the substrate bias is fixed at ground potential.

Claim 18

A memory as in claim 13 wherein the EEPROM devices are n-channel devices and the memory is operable in one of an erase mode, a program mode, and a read mode, the substrate bias having a value dependent on the mode of operation.

Claim 19

A memory as in claim 15 wherein: in an erase mode, the substrate bias is minus five volts, the first voltage is minus five volts, the second voltage is plus fifteen volts, and the third voltage is zero volts; and in a program mode, the substrate bias is zero volts, the first voltage is five volts, the second voltage is minus ten volts, and the third voltage is ten volts.

Claim 20

A memory as in claim 13 wherein each of the EEPROM devices between the first EEPROM device and the last EEPROM device in the series is connected to each neighboring EEPROM device with a source-drain interconnection.

Claim 21

A memory as in claim 13 wherein each of the EEPROM devices between the first EEPROM device and the last EEPROM device in the series is connected to one neighboring EEPROM device with a source-source interconnection and to another neighboring EEPROM device with a drain-drain interconnection.