Programmable logic module and architecture for field programmable gate array device

Claim 2

A combinatorial logic unit comprising: a cascaded multiplexer architecture having a plurality of multiplexer planes, each of said multiplexer planes including at least one multiplexer having inputs, at least one control input connected to at least one input node and at least one output; at least one multiplexer in a first of said multiplexer planes having said inputs connected to input nodes; inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane connected to said outputs of said at least one multiplexer in preceding multiplexer planes in said cascaded multiplexer architecture; at least one multiplexer in a last of said multiplexer planes having said at least one output connected to an output conductor; and at least one inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user-programmable interconnect elements.

Claim 3

The combinatorial logic unit of claim 1 further including an output buffer connected to said output conductor.

Claim 4

The combinatorial logic unit of claim 1 wherein said user-programmable interconnect elements are antifuses.

Claim 5

The combinatorial logic unit of claim 1 further including an output multiplexer having inputs connected to input nodes, an output connected to an output conductor and a control input connected to said output of said last multiplexer plane.

Claim 6

The combinatorial logic unit of claim 4 further including an output buffer connected to said output conductor.

Claim 7

The combinatorial logic unit of claim 1 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

Claim 8

The combinatorial logic unit of claim 6 wherein said logic gate is an AND gate.

Claim 9

The combinatorial logic unit of claim 6 wherein said logic gate is an OR gate.

Claim 10

The combinatorial logic unit of claim 1 further including a control multiplexer having a plurality of control multiplexer inputs connected to input nodes, a control input connected to an input node and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

Claim 11

The combinatorial logic unit of claim 9 wherein said at least one of said control multiplexer inputs is inverted.

Claim 12

The combinatorial logic unit of claim 1 wherein said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said outputs of said at least one multiplexer in an immediately preceding multiplexer plane in said cascaded multiplexer architecture.

Claim 13

The combinatorial logic unit of claim 1 wherein at least one of said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said input nodes.

Claim 14

A combinatorial logic unit comprising: N integrally ordered planes of multiplexers, wherein N is a positive integer, each of said multiplexers having a plurality of inputs, at least one control input connected to at least one input node, and an output; inputs of said multiplexers of a first one of said planes connected to input nodes; said outputs of said multiplexers of each plane up to a N-1 plane connected to said inputs of said multiplexers of a higher integrally ordered plane; at least one output of at least one multiplexer of an Nth plane connected to an output conductor; and at least one inverter, each inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user programmable interconnect elements.

Claim 15

A combinatorial logic unit comprising: N integrally ordered planes of multiplexers, wherein N is a positive integer, each of said multiplexers having a plurality of inputs, at least one control input connected to at least one input node, and an output; inputs of said multiplexers of a first one of said planes connected to input nodes; said outputs of said multiplexers of each plane up to a N-1 plane connected to said inputs of said multiplexers of a higher integrally ordered plane; at least one output of at least one multiplexer of an Nth plane connected to an output conductor; and at least one inverter, each inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user programmable interconnect elements.

Claim 16

The combinatorial logic unit of claim 13 further including an output buffer connected to said output conductor.

Claim 17

The combinatorial logic unit of claim 13 wherein said user-programmable interconnect elements are antifuses.

Claim 18

The combinatorial logic unit of claim 13 further including an output multiplexer having inputs connected to input nodes, an output connected to an output conductor and a control input connected to said output of said Nth multiplexer plane.

Claim 19

The combinatorial logic unit of claim 16 further including an output buffer connected to said output conductor.

Claim 20

The combinatorial logic unit of claim 13 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

Claim 21

The combinatorial logic unit of claim 18 wherein said logic gate is an AND gate.

Claim 22

The combinatorial logic unit of claim 18 wherein said logic gate is an OR gate.

Claim 23

The combinatorial logic unit of claim 13 further including a control multiplexer having a plurality of control multiplexer inputs connected to input nodes, a control input connected to an input node and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

Claim 24

The combinatorial logic unit of claim 21 wherein said at least one of said control multiplexer inputs is inverted.

Claim 25

The combinatorial logic unit of claim 13 wherein said outputs of said multiplexers of each plane up to a N-1 plane are connected to said inputs of said multiplexers of an immediately higher integrally ordered plane.

Claim 26

The combinatorial logic unit of claim 13 wherein at least one of said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said input nodes.

Claim 27

A combinatorial logic unit comprising: a multiplexer having a plurality of inputs connected to input nodes, at least one control input connected to an input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 28

A combinatorial logic unit comprising: a multiplexer having a plurality of inputs connected to input nodes, at least one control input connected to an input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 29

The combinatorial logic unit of claim 25 wherein said user-programmable interconnect elements are antifuses.

Claim 30

The combinatorial logic unit of claim 25 further including an output buffer connected to said output conductor.

Claim 31

The combinatorial logic unit of claim 25 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to at least one control input.

Claim 32

The combinatorial logic unit of claim 28 wherein said logic gate is an AND gate.

Claim 33

The combinatorial logic unit of claim 28 wherein said logic gate is an OR gate.

Claim 34

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 35

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 36

The combinatorial logic unit of claim 31 wherein said user-programmable interconnect elements are antifuses.

Claim 37

The combinatorial logic unit of claim 31 further including an output buffer connected to said output conductor.

Claim 38

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a sixth input node, and an output connected to an output conductor; and an inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes of said first and second multiplexers by user-programmable interconnect elements.

Claim 39

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a sixth input node, and an output connected to an output conductor; and an inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes of said first and second multiplexers by user-programmable interconnect elements.

Claim 40

The combinatorial logic unit of claim 34 wherein said user-programmable interconnect elements are antifuses.

Claim 41

The combinatorial logic unit of claim 34 further including an output buffer connected to said output conductor.

Claim 42

The combinatorial logic unit of claim 34 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said third input node.

Claim 43

The combinatorial logic unit of claim 34 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said sixth input node.

Claim 44

The combinatorial logic unit of claim 37 wherein said logic gate is an AND gate.

Claim 45

The combinatorial logic unit of claim 38 wherein said logic gate is an OR gate.

Claim 46

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input, and an output; a second multiplexer having a first input connected to a third input node, a second input connected to a fourth input node, a control input, and an output; a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input, and an output connected to an output conductor; a first control multiplexer having an input connected to a fifth input node, an inverting input connected to a sixth input node, a control input connected to a seventh input node and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a eighth input node, an inverting input connected to a ninth input node, a control input connected to a tenth input node and an output connected to said control input of said third multiplexer.

Claim 47

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input, and an output; a second multiplexer having a first input connected to a third input node, a second input connected to a fourth input node, a control input, and an output; a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input, and an output connected to an output conductor; a first control multiplexer having an input connected to a fifth input node, an inverting input connected to a sixth input node, a control input connected to a seventh input node and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a eighth input node, an inverting input connected to a ninth input node, a control input connected to a tenth input node and an output connected to said control input of said third multiplexer.

Claim 48

The combinatorial logic unit of claim 41 further including an output buffer connected to said output conductor.

Claim 49

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output; a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output; a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output; a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output; a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output connected to an output conductor; a plurality of interconnect conductors intersecting said input nodes of said first, second, third and fourth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements; and an inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

Claim 50

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output; a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output; a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output; a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output; a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output connected to an output conductor; a plurality of interconnect conductors intersecting said input nodes of said first, second, third and fourth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements; and an inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

Claim 51

The combinatorial logic unit of claim 43 wherein said user-programmable interconnect elements are antifuses.

Claim 52

The combinatorial logic unit of claim 43 further including an output buffer connected to said output conductor.

Claim 53

The combinatorial logic unit of claim 43 further including a logic gate having a first input connected to a twelfth input node, a second input connected to a thirteenth input node and an output connected to said tenth input node.

Claim 54

The combinatorial logic unit of claim 43 further including a logic gate having a first input connected to a twelfth input node, a second input connected to a thirteenth input node and an output connected to said eleventh input node.

Claim 55

The combinatorial logic unit of claim 46 wherein said logic gate is an AND gate.

Claim 56

The combinatorial logic unit of claim 47 wherein said logic gate is an OR gate.

Claim 57

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output; a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output; a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output; a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output; a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output; an eighth multiplexer having a first input connected to a twelfth input node, a second input connected to a thirteenth input node, a control input connected to the output of said seventh multiplexer, and an output connected to an output conductor; a plurality of interconnect conductors intersecting said input nodes of said first, second, third, fourth and eighth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements; a first inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements; and a second inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

Claim 58

A combinatorial logic unit comprising: a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output; a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output; a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output; a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output; a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output; a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output; a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output; an eighth multiplexer having a first input connected to a twelfth input node, a second input connected to a thirteenth input node, a control input connected to the output of said seventh multiplexer, and an output connected to an output conductor; a plurality of interconnect conductors intersecting said input nodes of said first, second, third, fourth and eighth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements; a first inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements; and a second inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

Claim 59

The combinatorial logic unit of claim 50 wherein said user-programmable interconnect elements are antifuses.

Claim 60

The combinatorial logic unit of claim 50 further including an output buffer connected to said output conductor.

Claim 61

The combinatorial logic unit of claim 50 further including a logic gate having a first input connected to a fourteenth input node, a second input connected to a fifteenth input node and an output connected to said tenth input node.

Claim 62

The combinatorial logic unit of claim 50 further including a logic gate having a first input connected to a fourteenth input node, a second input connected to a fifteenth input node and an output connected to said eleventh input node.

Claim 63

The combinatorial logic unit of claim 50 wherein said logic gate is an AND gate.

Claim 64

The combinatorial logic unit of claim 50 wherein said logic gate is an OR gate.

Claim 65

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a first control input connected to a fifth input node, a second control input connected to a sixth input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 66

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a first control input connected to a fifth input node, a second control input connected to a sixth input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 67

The combinatorial logic unit of claim 57 wherein said user-programmable interconnect elements are antifuses.

Claim 68

The combinatorial logic unit of claim 57 further including an output buffer connected to said output conductor.

Claim 69

The combinatorial logic unit of claim 57 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said fifth input node.

Claim 70

The combinatorial logic unit of claim 57 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said sixth input node.

Claim 71

The combinatorial logic unit of claim 60 wherein said logic gate is an AND gate.

Claim 72

The combinatorial logic unit of claim 61 wherein said logic gate is an OR gate.

Claim 73

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a fifth input connected to a fifth input node, a sixth input connected to a sixth input node, a seventh input connected to a seventh input node, an eighth input connected to an eighth input node, a first control input connected to a ninth input node, a second control input connected to a tenth input node, a third control input connected to an eleventh input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 74

A combinatorial logic unit comprising: a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a fifth input connected to a fifth input node, a sixth input connected to a sixth input node, a seventh input connected to a seventh input node, an eighth input connected to an eighth input node, a first control input connected to a ninth input node, a second control input connected to a tenth input node, a third control input connected to an eleventh input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

Claim 75

The combinatorial logic unit of claim 64 wherein said user-programmable interconnect elements are antifuses.

Claim 76

The combinatorial logic unit of claim 64 further including an output buffer connected to said output conductor.

Claim 77

The combinatorial logic unit of claim 64 further including a logic gate having a first input connected to a twelfth input node, a second input connected to an thirteenth input node and an output connected to said tenth input node.

Claim 78

The combinatorial logic unit of claim 64 further including a logic gate having a first input connected to a twelfth input node, a second input connected to an thirteenth input node and an output connected to said eleventh input node.

Claim 79

The combinatorial logic unit of claim 67 wherein said logic gate is an AND gate.

Claim 80

The combinatorial logic unit of claim 68 wherein said logic gate is an OR gate.