Computer processing element having first and second functional units accessing shared memory output port on prioritized basis

Claim 2

A processing element for a computer system, said processing element comprising: memory means having a limited number of input ports and a limited number of output ports, the memory means having at least two input ports and at least two output ports; at least first and second functional unit means, said first functional unit means, having M inputs, for performing a first function on data applied to at least one input thereof and for generating a result at its output, and said second functional unit means, having N inputs, for performing a second function on data applied to at least one input thereof and generating a result at its output; multiplexer means for connecting a single memory output port to inputs of both the first and second functional units to permit sharing therebetween; and data path means for forwarding the output result of the first functional unit to an input of the second functional unit while bypassing the memory means, wherein, said memory means having less than M+N output ports, where M and N are integers, wherein the functional units are prioritized to thereby give the one functional unit having priority access to the single memory output port in the event that the functional units attempt to concurrently execute instructions calling for access to the single memory output port.

Claim 3

The processing element of claim 1 which further comprises: first input/output (I/O) means having inputs for receiving data and an output for transmitting data; and second I/O means having inputs for receiving data and an output for transmitting data, wherein at least one of the memory output ports is connected to both an input of one of the functional units and to an input of one of the I/O means.

Claim 4

The processing element of claim 2 wherein the data path means further comprises: means for forwarding an output of one of the I/O means an input of at least one or more of the functional unit means.

Claim 5

The processing element of claim 3 wherein said multiplexer means comprises: a series of multiplexer devices, at least one multiplexer device for each input of each functional unit and for each input of each I/O means, each multiplexer device having a plurality of inputs and an output connected to its respective functional unit or I/O means, wherein the inputs of the multiplexer device which is connected to the first functional unit are coupled to: a) an output port from the memory means; b) an output from the second functional unit; and c) an output from one of the I/O means

Claim 6

The processing element of claim 4 wherein the inputs of the multiplexer device connected to the first I/O means are connected to a plurality of output ports of the memory means.

Claim 7

The processing element of claim 5 wherein said data path means further comprises: a second series of multiplexer devices for selectively connecting outputs of the functional units and I/O means to input ports of the memory means.

Claim 8

The processing element of claim 6 wherein said second series of multiplexer devices comprises: a first multiplexer device having inputs connected to the outputs of the first and second I/O means and having an output connected to one of the memory input ports; a second multiplexer device having inputs connected to an output of the first I/O means and one of the functional units, with an output thereof being coupled to a second input port of the memory means; and a third multiplexer device having inputs coupled to an output of the second I/O means and the other functional unit, with an output thereof being coupled to a third input port of the memory means.

Claim 9

A computer system comprising: a host computer; a co-processor array having a plurality of mesh connected processing elements (PEs), a controller for generating a very long instructions word (VLIW) for controlling the operations of the processing elements, said processing elements performing the same instruction on multiple data associated with each processing element, each of said processing elements including: random access memory means having a plurality of memory locations for storing data, said memory means having a limited number of input ports and a limited number of output ports, the memory means having at least two input ports and at least two output ports at least first and second functional unit means, said first functional unit means, having M inputs, for performing a first function on data applied to at least one of its input and for generating a result at its output, and said second functional unit means, having N inputs, for performing a second function on data applied to its input and generating a result at its output; multiplexer means for selectively connecting a single memory output port to inputs of both the first and second functional units; and data path means for forwarding the output result of the first functional unit to an input of the second functional unit while bypassing the memory means, wherein, said memory means having less than M+N output ports, where M and N are integers, wherein said functional units are given access to said single memory output port on prioritized basis.

Claim 10

A computer system comprising: a host computer; a co-processor array having a plurality of mesh connected processing elements (PEs), a controller for generating a very long instructions word (VLIW) for controlling the operations of the processing elements, said processing elements performing the same instruction on multiple data associated with each processing element, each of said processing elements including: random access memory means having a plurality of memory locations for storing data, said memory means having a limited number of input ports and a limited number of output ports, the memory means having at least two input ports and at least two output ports at least first and second functional unit means, said first functional unit means, having M inputs, for performing a first function on data applied to at least one of its input and for generating a result at its output, and said second functional unit means, having N inputs, for performing a second function on data applied to its input and generating a result at its output; multiplexer means for selectively connecting a single memory output port to inputs of both the first and second functional units; and data path means for forwarding the output result of the first functional unit to an input of the second functional unit while bypassing the memory means, wherein, said memory means having less than M+N output ports, where M and N are integers, wherein said functional units are given access to said single memory output port on prioritized basis.

Claim 11

The system of claim 8 wherein said first functional unit comprises multiplier means for multiplying together two operands applied to two of its inputs; and said second functional unit comprises arithmetic logic unit (ALU) means for performing arithmetic functions on operands applied to two of its inputs.

Claim 12

The system of claim 9 wherein said multiplexer means comprises: a first multiplexer device coupled to a first input of the multiplier means; a second multiplexer device connected to a second input of the multiplier means; a third multiplexer device connected to a first input of the ALU means; and a fourth multiplexer device connected to a second input of the ALU means.

Claim 13

The system of claim 10 which further comprises: first input/output (I/O) means having an input for receiving data and an output for transmitting data; and second I/O means having an input for receiving data and an output for transmitting data; and wherein at least one of the memory output ports is connected to both an input of one of the functional units and to an input of one of the I/O means.

Claim 14

The system of claim 11 wherein said data path means further comprises: a second series of multiplexer devices for selectively connecting outputs of the functional units and I/O means to input ports of the memory.

Claim 15

The system of claim 12 wherein said second series of multiplexer devices comprises: a first multiplexer having inputs connected to the outputs of the first and second I/O means and having an output connected to one of the memory input ports; a second multiplexer device having inputs connected to an output of the first I/O means and one of the functional units, with an output thereof being coupled to a second input port of the memory means; and a third device having inputs coupled to an output of the second I/O means and the other functional unit, with an output thereof being coupled to a third input port of the memory means.

Claim 16

The system of claim 13 wherein the memory means has five output ports coupled to the multiplexer means, and three input ports coupled to the second series of multiplexer devices.

Claim 17

The processing unit of claim 14 wherein the multiplier means, arithmetic logic unit means, first input/output means and second input/output means are given access to shared memory ports on prioritized basis.