US5486714A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trench EEPROM with tunnel oxide in trench
Assignee: United Microelectronics Corp
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Filing: 1995-05-22
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Granted: 1996-01-23
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Expires: 2015-05-22
Abstract
Abstract A floating gate EPROM has surface source and drain regions, with a trench between the source and drain regions containing the floating and control gates. A thin tunneling oxide layer is located at the bottom of the trench and on the sidewalls of the trench adjacent the source and drain regions, with thicker gate oxide elsewhere in the trench.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:21
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
The Flash EEPROM memory comprising: a stacked polysilicon gate structure in a trench within a semiconductor substrate and extending above said semiconductor substrate; source and drain regions on either side of said stacked polysilicon gate structure at the surface of said substrate; a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench; a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer; a polysilicon floating gate at the base of said stacked polysilicon gate structure; an interpoly dielectric layer overlying said polysilicon floating gate; and a polysilicon control gate overlying said interpoly dielectric layer.
Claim 2
Dependent Claim
134 words
The Flash EEPROM memory comprising: a stacked polysilicon gate structure in a trench within a semiconductor substrate and extending above said semiconductor substrate; source and drain regions on either side of said stacked polysilicon gate structure at the surface of said substrate; a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench; a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer; a polysilicon floating gate at the base of said stacked polysilicon gate structure; an interpoly dielectric layer overlying said polysilicon floating gate; and a polysilicon control gate overlying said interpoly dielectric layer.
Claim 3
Dependent Claim
19 words
The device of claim 1 wherein said tunnel oxide has a thickness of between about 60 to 100 Angstroms.
Claim 4
Dependent Claim
20 words
The device of claim 1 wherein said thick gate oxide layer is between about 200 to 300 Angstroms in thickness.
Claim 5
Dependent Claim
18 words
The device of claim 1 wherein said interpoly dielectric layer is composed of ONO (silicon oxide-silicon nitride-silicon oxide).
Claim 6
Dependent Claim
112 words
The Flash EEPROM memory comprising: a polysilicon floating gate within a trench within a semiconductor substrate; source and drain regions on either side of said floating gate at the surface of said substrate; a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench; a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer; an interpoly dielectric layer overlying said polysilicon floating gate; and a polysilicon control gate overlying said interpoly dielectric layer.
Claim 7
Dependent Claim
112 words
The Flash EEPROM memory comprising: a polysilicon floating gate within a trench within a semiconductor substrate; source and drain regions on either side of said floating gate at the surface of said substrate; a thin tunnel oxide layer overlying said source and drain regions, on the sidewalls of the upper portions of said trench contacting said source and drain regions, and at a small center portion of the bottom of said trench; a thick gate oxide layer on the sidewalls and bottom of said trench not covered by said thin tunnel oxide layer; an interpoly dielectric layer overlying said polysilicon floating gate; and a polysilicon control gate overlying said interpoly dielectric layer.
Claim 8
Dependent Claim
19 words
The device of claim 5 wherein said tunnel oxide has a thickness of between about 60 to 100 Angstroms.
Claim 9
Dependent Claim
20 words
The device of claim 5 wherein said thick gate oxide layer is between about 200 to 300 Angstroms in thickness.
Claim 10
Dependent Claim
18 words
The device of claim 5 wherein said interpoly dielectric layer is composed of ONO (silicon oxide-silicon nitride-silicon oxide).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |