Semiconductor memory device having high speed sense amplifier

Claim 2

A semiconductor memory device comprising: a memory cell array including a plurality of memory cells, a plurality of word lines and a plurality of digit lines, each of said memory cells being coupled to one of said word lines and one of said digit lines; an inverting amplifier having an input node and an output node; a column selector selecting one of said digit lines in response to a column selection signal and coupling said one of said digit lines to the input node of said inverting amplifier; a first transistor of a first channel type connected between the input node of said inverting amplifier and a circuit node and having a gate connected to the output node of said inverting amplifier; a precharge transistor of a second channel type having a source coupled to a power supply line and a gate and a drain coupled to said circuit node, said first channel type being opposite to said second channel type; an impedance element coupled between said power supply line and said circuit node; and an amplifier having a first input end coupled to said circuit node and a second input end supplied with a reference voltage.

Claim 3

The semiconductor memory device as claimed in claim 1, wherein said impedance element comprises a third transistor which is an enhancement type and having a threshold voltage smaller than a threshold voltage of said first transistor, and a gate coupled to said power supply line.

Claim 4

The semiconductor memory device as claimed in claim 1, wherein said impedance element comprises a depletion type transistor having a gate coupled to said power supply line.

Claim 5

The semiconductor memory device as claimed in claim 1, wherein each of said memory cells comprises an insulated gate transistor which, by a read-out voltage supplied thereto, is rendered conductive or kept non-conductive in accordance with data stored therein, and said reference voltage has an intermediate level between a first level that is obtained at said circuit node when a memory cell being rendered conductive is coupled to said one of said digit lines and a second level that is obtained at said circuit node when a memory cell being kept non-conductive is coupled to said one of said digit lines.

Claim 6

A semiconductor memory comprising: a sense node, a precharging transistor coupled between a power supply line and said sense node and precharging said sense node to a precharge level that is smaller than a power voltage on said power supply line by a threshold voltage of said precharging transistor, an impedance element coupled between said power supply line and said circuit node and changing said circuit node from said precharge level to a first voltage level that is larger than said precharge level when a memory cell storing one of a binary data is coupled to said circuit node and to a second voltage level that is smaller than said first voltage level when a memory cell storing the other of said binary data is coupled to said circuit node, a reference voltage generator generating a reference voltage that is intermediate between said first and second voltage levels, a comparator comparing a voltage level of said circuit node with said reference voltage, and a coupling circuit coupling said memory cell to said circuit node, said coupling circuit comprising a coupling transistor having a source-drain path connected between said circuit node and said memory cell and an inverter having an input node connected to said memory cell and an output node connected to a gate of said coupling transistor, said coupling transistor having a channel type opposite to a channel type of said precharge transistor, said impedance element comprising a load transistor of a channel type equal to the channel type of said coupling transistor and opposite to the channel type of said precharge transistor.

Claim 7

A semiconductor memory comprising: a sense node, a precharging transistor coupled between a power supply line and said sense node and precharging said sense node to a precharge level that is smaller than a power voltage on said power supply line by a threshold voltage of said precharging transistor, an impedance element coupled between said power supply line and said circuit node and changing said circuit node from said precharge level to a first voltage level that is larger than said precharge level when a memory cell storing one of a binary data is coupled to said circuit node and to a second voltage level that is smaller than said first voltage level when a memory cell storing the other of said binary data is coupled to said circuit node, a reference voltage generator generating a reference voltage that is intermediate between said first and second voltage levels, a comparator comparing a voltage level of said circuit node with said reference voltage, and a coupling circuit coupling said memory cell to said circuit node, said coupling circuit comprising a coupling transistor having a source-drain path connected between said circuit node and said memory cell and an inverter having an input node connected to said memory cell and an output node connected to a gate of said coupling transistor, said coupling transistor having a channel type opposite to a channel type of said precharge transistor, said impedance element comprising a load transistor of a channel type equal to the channel type of said coupling transistor and opposite to the channel type of said precharge transistor.

Claim 8

The memory device as claimed in claim 5, wherein said precharging transistor is of a P-channel type and has a source coupled to said power supply line and a gate and a drain coupled to said circuit node, and each of said coupling transistor and said load transistor is of an N-channel type.

Claim 9

The memory device as claimed in claim 6, wherein said load transistor is an N-channel transistor having a threshold voltage smaller in absolute value then a threshold voltage of said precharging transistor and a gate coupled to said power supply line.

Claim 10

The memory device as claimed in claim 6, wherein said load transistor is an N-channel depletion transistor.

Claim 11

The memory device as claimed in claim 1, wherein said first channel type is an N-channel type and said second channel type is a P-channel type.