Method of manufacturing self-aligned bit-line during EPROM fabrication

Claim 1

A method for manufacturing EPROM integrated circuit memory devices which comprises the steps of: providing a semiconductor substrate having devices therein to which electrical connections are to be made, forming a tunnel oxide layer on said substrate, forming a blanket, doped, polysilicon layer over said tunnel oxide layer on said substrate, forming an interelectrode dielectric layer over said blanket, doped, polysilicon layer, forming a blanket polycide layer over said interelectrode dielectric layer, forming a silicon dioxide dielectric layer over said blanket polycide layer, forming a silicon nitride (Si 3 N 4 ) layer over said silicon dioxide layer, forming a source/drain mask over said silicon nitride layer with source/drain trench openings therein said source trench openings being substantially more narrow than said drain trench openings, etching to form EPROM gate electrode stacks with trench spaces between said stacks in an array of said stacks, said stacks being formed by said silicon nitride (Si 3 N 4 ) layer, said silicon dioxide dielectric layer, said polycide layer, said interelectrode dielectric layer, and said polysilicon layer down to said tunnel oxide layer, said EPROM gate stacks having sidewalls with said trench spaces therebetween, said trench spaces between said sidewalls including source trench spaces over said source regions and drain trench spaces over said drain regions, said source trench spaces being substantially more narrow than said drain trench spaces, ion implanting of source/drain dopant ions between said stacks forming alternating source regions and drain regions below said spaces between said sidewalls, forming spacer dielectric structures adjacent to said sidewalls over said drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling said spaces over said source regions, forming a blanket dielectric layer over said stacks, said spaces and said sidewalls, etching bit-line conductor openings across said device and drain trench openings through said blanket dielectric layer down to said drain regions, forming a bit-line conductive metal blanket layer over said device extending down into contact with said drain regions through said drain trench openings, etching back said conductive metal blanket layer leaving conductor lines in contact with said drain regions, whereby said EPROM memory devices include a self-aligned bit-line structure formed simultaneously with electrical contacts to the drain electrodes.

Claim 2

A method for manufacturing EPROM integrated circuit memory devices which comprises the steps of: providing a semiconductor substrate having devices therein to which electrical connections are to be made, forming a tunnel oxide layer on said substrate, forming a blanket, doped, polysilicon layer over said tunnel oxide layer on said substrate, forming an interelectrode dielectric layer over said blanket, doped, polysilicon layer, forming a blanket polycide layer over said interelectrode dielectric layer, forming a silicon dioxide dielectric layer over said blanket polycide layer, forming a silicon nitride (Si 3 N 4 ) layer over said silicon dioxide layer, forming a source/drain mask over said silicon nitride layer with source/drain trench openings therein said source trench openings being substantially more narrow than said drain trench openings, etching to form EPROM gate electrode stacks with trench spaces between said stacks in an array of said stacks, said stacks being formed by said silicon nitride (Si 3 N 4 ) layer, said silicon dioxide dielectric layer, said polycide layer, said interelectrode dielectric layer, and said polysilicon layer down to said tunnel oxide layer, said EPROM gate stacks having sidewalls with said trench spaces therebetween, said trench spaces between said sidewalls including source trench spaces over said source regions and drain trench spaces over said drain regions, said source trench spaces being substantially more narrow than said drain trench spaces, ion implanting of source/drain dopant ions between said stacks forming alternating source regions and drain regions below said spaces between said sidewalls, forming spacer dielectric structures adjacent to said sidewalls over said drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling said spaces over said source regions, forming a blanket dielectric layer over said stacks, said spaces and said sidewalls, etching bit-line conductor openings across said device and drain trench openings through said blanket dielectric layer down to said drain regions, forming a bit-line conductive metal blanket layer over said device extending down into contact with said drain regions through said drain trench openings, etching back said conductive metal blanket layer leaving conductor lines in contact with said drain regions, whereby said EPROM memory devices include a self-aligned bit-line structure formed simultaneously with electrical contacts to the drain electrodes.

Claim 21

A method for manufacturing EPROM integrated circuit memory devices which comprises the steps of: providing a semiconductor substrate having devices therein to which electrical connections are to be made, forming a tunnel oxide layer on said substrate, forming a blanket, doped, polysilicon layer over said tunnel oxide layer on said substrate, forming an interelectrode dielectric layer over said blanket, doped, polysilicon layer, forming a blanket polycide layer over said interelectrode dielectric layer, forming a silicon dioxide dielectric layer over said blanket polycide layer said silicon dioxide layer comprises a TEOS (tetraethylorthosilicate) dielectric layer at a temperature between about 650° and 750° C. in an LPCVD reactor by decomposing tetraethoxysilane, Si(OC 2 H 5 ) 4 vaporized from a liquid source producing a complex mixture of organic and organosilicon compounds above said blanket polycide layer, forming a silicon nitride (Si 3 N 4 ) layer over said silicon dioxide layer, forming a source/drain mask over said silicon nitride layer with source/drain trench openings therein said source trench openings being substantially more narrow than said drain trench openings, etching in a self-aligned source and drain etching process to form EPROM gate electrode stacks with trench spaces between said stacks in an array of said stacks, said stacks being formed by said silicon nitride (Si 3 N 4 ) layer, said silicon dioxide dielectric layer, said polycide layer, said interelectrode dielectric layer, and said polysilicon layer down to said tunnel oxide layer, said stacks having sidewalls with said trench spaces therebetween, said trench spaces between said sidewalls including source trench spaces over said source regions and drain trench spaces over said drain regions, said source trench spaces being substantially more narrow than said drain trench spaces, ion implantation of source/drain dopant ions with an MDD N+ ion implanting process between said stacks forming alternating source regions and drain regions below said spaces between said sidewalls, forming spacer dielectric structures adjacent to said sidewalls over said drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling said spaces over said source regions, performing an additional N+ implant between said spacers into said drain regions, forming a blanket dielectric layer over said stacks, said spaces and said sidewalls, said blanket dielectric layer comprising BPTEOS, etching drain bit-line openings down to said drain regions drain regions through said blanket dielectric layer and said tunnel oxide layer over said drain regions between said spacers, forming a barrier metal layer of titanium/titanium nitride over the exposed surfaces of said drain regions, forming a conductive metal blanket layer over said device extending down into contact with said drain regions through said bit-line openings, etching back said conductive metal blanket layer leaving said bit-lines extending across said device and down into contact with said drain regions, and whereby said EPROM memory devices include a self-aligned bit-line structure formed simultaneously with electrical contacts to the drain electrodes.

Claim 22

A method for manufacturing EPROM integrated circuit memory devices which comprises the steps of: providing a semiconductor substrate having devices therein to which electrical connections are to be made, forming a tunnel oxide layer on said substrate, forming a blanket, doped, polysilicon layer over said tunnel oxide layer on said substrate, forming an interelectrode dielectric layer over said blanket, doped, polysilicon layer, forming a blanket polycide layer over said interelectrode dielectric layer, forming a silicon dioxide dielectric layer over said blanket polycide layer said silicon dioxide layer comprises a TEOS (tetraethylorthosilicate) dielectric layer at a temperature between about 650° and 750° C. in an LPCVD reactor by decomposing tetraethoxysilane, Si(OC 2 H 5 ) 4 vaporized from a liquid source producing a complex mixture of organic and organosilicon compounds above said blanket polycide layer, forming a silicon nitride (Si 3 N 4 ) layer over said silicon dioxide layer, forming a source/drain mask over said silicon nitride layer with source/drain trench openings therein said source trench openings being substantially more narrow than said drain trench openings, etching in a self-aligned source and drain etching process to form EPROM gate electrode stacks with trench spaces between said stacks in an array of said stacks, said stacks being formed by said silicon nitride (Si 3 N 4 ) layer, said silicon dioxide dielectric layer, said polycide layer, said interelectrode dielectric layer, and said polysilicon layer down to said tunnel oxide layer, said stacks having sidewalls with said trench spaces therebetween, said trench spaces between said sidewalls including source trench spaces over said source regions and drain trench spaces over said drain regions, said source trench spaces being substantially more narrow than said drain trench spaces, ion implantation of source/drain dopant ions with an MDD N+ ion implanting process between said stacks forming alternating source regions and drain regions below said spaces between said sidewalls, forming spacer dielectric structures adjacent to said sidewalls over said drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling said spaces over said source regions, performing an additional N+ implant between said spacers into said drain regions, forming a blanket dielectric layer over said stacks, said spaces and said sidewalls, said blanket dielectric layer comprising BPTEOS, etching drain bit-line openings down to said drain regions drain regions through said blanket dielectric layer and said tunnel oxide layer over said drain regions between said spacers, forming a barrier metal layer of titanium/titanium nitride over the exposed surfaces of said drain regions, forming a conductive metal blanket layer over said device extending down into contact with said drain regions through said bit-line openings, etching back said conductive metal blanket layer leaving said bit-lines extending across said device and down into contact with said drain regions, and whereby said EPROM memory devices include a self-aligned bit-line structure formed simultaneously with electrical contacts to the drain electrodes.