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US5652905A
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US
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Data processing unit
Assignee: Fujitsu Ltd
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Filing: 1995-06-05
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Granted: 1997-07-29
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Expires: 2015-06-05
Abstract
Abstract A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.
Inventors
- 👤 Naoki Shinjo
- 👤 Shigeru Nagasawa
- 👤 Masayuki Ikeda
- 👤 Haruhiko Ueno
- 👤 Teruo Utsumi
- 👤 Kazushige Kobayakawa
- 👤 Masami Dewa
- 👤 Kenichi Ishizaka
- 👤 Tadao Amada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:51
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
265 words
A data processing unit adapted to exchange data with another data processing unit via a network, said data processing unit comprising: main storage means for storing programs and data, and comprising counter means for storing a content; instruction processor means, coupled to said main storage means, for issuing transfer requests by executing programs stored in said main storage means; and transfer processor means, coupled to said main storage means and said instruction processor means, for enqueuing the transfer requests from said instruction processor means into a transfer request queue, and for carrying out a transfer process between said main storage means and the network based on each transfer request which is obtained from the transfer request queue, said transfer processor means comprising: first register storing means for storing an expected value of the content of said counter means for an arbitrary process, and second register storing means for storing a flag indicating whether an interrupt has been generated with respect to said instruction processor means, said transfer processor means generating the interrupt with respect to said instruction processor means and setting the flag in said second register means when the content of said counter means and the expected value in said first register means match for the arbitrary process, wherein the content is updated by said transfer processor means every time the transfer process is carried out based on the transfer request and is accessible by said instruction processor means, and wherein said instruction processor means recognizes an end of the transfer process by said transfer processor means from the content of said counter means.
Claim 2
Dependent Claim
265 words
A data processing unit adapted to exchange data with another data processing unit via a network, said data processing unit comprising: main storage means for storing programs and data, and comprising counter means for storing a content; instruction processor means, coupled to said main storage means, for issuing transfer requests by executing programs stored in said main storage means; and transfer processor means, coupled to said main storage means and said instruction processor means, for enqueuing the transfer requests from said instruction processor means into a transfer request queue, and for carrying out a transfer process between said main storage means and the network based on each transfer request which is obtained from the transfer request queue, said transfer processor means comprising: first register storing means for storing an expected value of the content of said counter means for an arbitrary process, and second register storing means for storing a flag indicating whether an interrupt has been generated with respect to said instruction processor means, said transfer processor means generating the interrupt with respect to said instruction processor means and setting the flag in said second register means when the content of said counter means and the expected value in said first register means match for the arbitrary process, wherein the content is updated by said transfer processor means every time the transfer process is carried out based on the transfer request and is accessible by said instruction processor means, and wherein said instruction processor means recognizes an end of the transfer process by said transfer processor means from the content of said counter means.
Claim 3
Dependent Claim
23 words
The data processing unit as claimed in claim 1, wherein the arbitrary process corresponds to one or a plurality of transfer request queues.
Claim 4
Dependent Claim
35 words
The data processing unit as claimed in claim 1, wherein said transfer processor means includes: third register means for storing an address of said counter means in said main storage means for the arbitrary process.
Claim 5
Dependent Claim
37 words
The data processing unit as claimed in claim 3, wherein said instruction processor means sets the expected value and the address of said counter means for the arbitrary process in said first and third register means, respectively.
Claim 6
Dependent Claim
71 words
The data processing unit as claimed in claim 3, wherein: said transfer processor means enqueues a plurality of transfer request queues; a plurality of said counter means are provided in correspondence with the plurality of transfer request queues; a plurality of said first and third register means are respectively provided in correspondence with the plurality of processes, each of said processes corresponding to one or a plurality of transfer request queues.
Claim 7
Dependent Claim
40 words
The data processing unit as claimed in claim 1, wherein said counter means stores the content which is updated every time at least one of transmission and reception is carried out by the transfer process based on the transfer request.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-28 | 2001-01-27 | 2001-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-28 | 2005-01-27 | 2005-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-28 | 2009-01-27 | 2009-07-29 | $7700.00 | Window Closed / Lapsed |