Nonvolatile memory cell formed using self aligned source implant

Claim 1

In a method for forming a high density array of floating gate memory cells in a semiconductor substrate, where each cell comprises source, channel and drain semiconductor regions in the substrate, and a first dielectric, floating gate, second dielectric and control gate, formed overlying the channel, the source and drain regions defining a controlled current path through the channel which is rendered conductive in response to a voltage above a gate threshold level being applied to the control gate, and the cells are arranged in a series of rows and columns, with respective insulative material regions disposed between adjacent columns of cells, each row has an associated word line electrically connecting the gate structures of each of the cells within the row, each column has an associated bit line electrically connecting the drain semiconductor regions of each of the cells within the column, and the source region of each cell within the array electrically is connected by a common line; the improvement wherein the common line connecting the source regions is formed by high energy implantation of dopants through portions of the insulative material between sources of corresponding cells in adjacent columns.

Claim 10

A method for forming a high density array of rows and columns of floating gate memory cells in a semiconductor substrate, comprising the steps of: forming parallel strips of field oxide to separate regions of substrate corresponding to columns of cells in the array; forming parallel stacked-gate-word-line structures disposed perpendicular to and extending over the field oxide strips, spaced apart by a first distance; selectively forming doped source and drain regions in the substrate regions corresponding to columns of cells in alignment with the stacked-gate-word-line structures; and forming, by high energy implantation of dopants through the portions of the field oxide strips between source regions of corresponding cells in adjacent columns, interconnection regions effecting electrical connection between the source regions.

Claim 11

A method for forming a high density array of rows and columns of floating gate memory cells in a semiconductor substrate, comprising the steps of: forming parallel strips of field oxide to separate regions of substrate corresponding to columns of cells in the array; forming parallel stacked-gate-word-line structures disposed perpendicular to and extending over the field oxide strips, spaced apart by a first distance; selectively forming doped source and drain regions in the substrate regions corresponding to columns of cells in alignment with the stacked-gate-word-line structures; and forming, by high energy implantation of dopants through the portions of the field oxide strips between source regions of corresponding cells in adjacent columns, interconnection regions effecting electrical connection between the source regions.