Process for forming a semiconductor device having field isolation

Claim 2

A process for forming a semiconductor device comprising the steps of: forming a first trench within a first region of a substrate, wherein: the first trench defines a single mesa within the first region; and the first trench has a width no greater than about two microns along opposite sides of the single mesa; forming a fill layer within the first trench; and removing a portion of the fill layer to form a first field isolation region having a width of at least ten microns, wherein the first field isolation region has a planar surface and lies within the first region and includes a remaining portion of the fill layer and the single mesa but no other mesa.

Claim 3

The process of claim 1, further comprising steps of: forming a dielectric layer over the first field isolation region including the single mesa; and forming a conductor over the first field isolation region, wherein the conductor lies within 500 angstroms of the single mesa within the first field isolation region.

Claim 4

The process of claim 1, wherein: the step of forming the first trench also forms a second trench for a second field isolation region; the step of forming the fill layer is performed such that the fill layer is formed within the second trench; and the step of removing is performed to form the second field isolation region that does not include a mesa.

Claim 5

The process of claim 1, further comprising a step of forming an etch-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by anisotropically etching the fill layer overlying the single mesa until the etch-stop layer is exposed.

Claim 6

The process of claim 1, further comprising a step of forming a polish-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by polishing the fill layer overlying the single mesa until the polish-stop layer is exposed.

Claim 7

A process for forming a semiconductor device comprising the steps of: forming a first trench and a second trench within a substrate to define a first component region, wherein: the first component region has a first side and a second side opposite the first side; the first trench lies adjacent to the first side of the first component region; second component region lies adjacent to the first trench on a side of the first trench opposite the first component region; and the second trench lies adjacent to the second side of the first component region and defines a plurality of mesas; and forming a fill layer within the first and second trenches to form a first field isolation region and a second field isolation region, wherein: the first field isolation region lies at least partly within the first trench; the second field isolation region lies at least partly within the second trench and includes the plurality of mesas; and the fill layer laterally surrounds the plurality of mesas; and removing a portion of the fill layer to form a first field isolation region within the first trench and a second field isolation region within the second trench, wherein the first field isolation region includes a remaining portion of the fill layer but no mesa, and the second field isolation region includes a remaining portion of the fill layer and the plurality of mesas.

Claim 8

A process for forming a semiconductor device comprising the steps of: forming a first trench and a second trench within a substrate to define a first component region, wherein: the first component region has a first side and a second side opposite the first side; the first trench lies adjacent to the first side of the first component region; second component region lies adjacent to the first trench on a side of the first trench opposite the first component region; and the second trench lies adjacent to the second side of the first component region and defines a plurality of mesas; and forming a fill layer within the first and second trenches to form a first field isolation region and a second field isolation region, wherein: the first field isolation region lies at least partly within the first trench; the second field isolation region lies at least partly within the second trench and includes the plurality of mesas; and the fill layer laterally surrounds the plurality of mesas; and removing a portion of the fill layer to form a first field isolation region within the first trench and a second field isolation region within the second trench, wherein the first field isolation region includes a remaining portion of the fill layer but no mesa, and the second field isolation region includes a remaining portion of the fill layer and the plurality of mesas.

Claim 9

The process of claim 6, wherein each of the first and second trenches has a width no wider than two microns.

Claim 10

The process of claim 6, wherein: the step of forming the first and second trenches forms a plurality of the second trenches that define a plurality of the mesas surrounded by the second trenches; and at least some of the mesas surrounded by the second trenches have shapes such that, from a plan view, those mesas form a first symbol and a second symbol that is different from the first symbol the semiconductor device includes an identifier selected from a part number and a mask set; and the identifier includes the plurality of symbols.

Claim 11

The process of claim 8, wherein the identifier is a part number.

Claim 12

The process of claim 6, further comprising a step of forming an etch-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by anisotropically etching the fill layer overlying the plurality of mesas until the etch-stop layer is exposed.

Claim 13

The process of claim 6, further comprising a step of forming a polish-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by polishing the fill layer overlying the plurality of mesas until the polish-stop layer is exposed.

Claim 14

The process of claim 6 further comprising a step of forming a conductor over the second field isolation region, wherein the conductor lies within 500 angstroms of at least one mesa of the plurality of mesas within the second field isolation region.

Claim 15

A process for forming a semiconductor device comprising the steps of: forming a trench within the substrate, wherein the trench defines a mesa; forming a fill layer within the trench; removing a portion of the fill layer to form a first field isolation region having a planar surface, wherein the first field isolation region includes the fill layer and the mesa; and forming a conductor over the first field isolation region, wherein the conductor lies within 500 angstroms of the mesa within the first field isolation region.

Claim 16

A process for forming a semiconductor device comprising the steps of: forming a trench within the substrate, wherein the trench defines a mesa; forming a fill layer within the trench; removing a portion of the fill layer to form a first field isolation region having a planar surface, wherein the first field isolation region includes the fill layer and the mesa; and forming a conductor over the first field isolation region, wherein the conductor lies within 500 angstroms of the mesa within the first field isolation region.

Claim 17

The process of claim 13, wherein: the step of forming the trench forms another trench, wherein a component region lies between the trenches; and the step of forming the fill layer is performed such that the fill layer lies within the another trench, wherein a second field isolation region includes the fill layer within the another trench but does not include a mesa.

Claim 18

The process of claim 13, wherein: the step of forming the trench defines a plurality of the mesas within the first field isolation region, wherein any one of the mesas within the first field isolation region lies within five microns of a different mesa within the first field isolation region.

Claim 19

The process of claim 13, wherein: the step of forming the trench forms a plurality of the mesas within the first field isolation region; and at least some of the mesas within the first field isolation region have shapes such that, from a plan view, those mesas form a first symbol and a second symbol that is different from the first symbol.

Claim 20

The process of claim 13, further comprising a step of forming an etch-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by anisotropically etching the fill layer overlying the mesa until the etch-stop layer is exposed.

Claim 21

The process of claim 13, further comprising a step of forming a polish-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is preformed by polishing the fill layer overlying the mesa until the polish layer is exposed.

Claim 22

A process for forming a semiconductor device comprising the steps of: forming a plurality of first trenches within the substrate, wherein: the plurality of first trenches defines a plurality of mesas that, from a plan view, form a plurality of symbols; the semiconductor device includes an identifier selected from a part number and a mask set; and the identifier includes the plurality of symbols; forming a fill layer within the plurality of first trenches; and removing a portion of the fill layer to form a first field isolation region having a planar surface, wherein the first field isolation region includes a remaining portion of the fill layer and the plurality of mesas.

Claim 23

A process for forming a semiconductor device comprising the steps of: forming a plurality of first trenches within the substrate, wherein: the plurality of first trenches defines a plurality of mesas that, from a plan view, form a plurality of symbols; the semiconductor device includes an identifier selected from a part number and a mask set; and the identifier includes the plurality of symbols; forming a fill layer within the plurality of first trenches; and removing a portion of the fill layer to form a first field isolation region having a planar surface, wherein the first field isolation region includes a remaining portion of the fill layer and the plurality of mesas.

Claim 24

The process of claim 19, further comprising a step of forming a conductor over the first field isolation region, wherein the conductor lies within 500 angstroms of at least one mesa of the plurality of mesas within the first field isolation region.

Claim 25

The process of claim 19, wherein the identifies is the part number.

Claim 26

The process of claim 19, wherein: the step of forming the plurality of first trenches forms a second trench, wherein a component region lies between the plurality of first trenches and the second trench; and the step of forming the fill layer is performed such that the fill layer lies within the second trench, wherein a second field isolation region includes the fill layer within the second trench but does not include a mesa.

Claim 27

The process of claim 19, further comprising a step of forming an etch-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by anisotropically etching the fill layer overlying the plurality of mesas until the etch-stop layer is exposed.

Claim 28

The process of claim 19, further comprising a step of forming a polish-stop layer over the substrate before the step of forming the fill layer, wherein the step of removing is performed by polishing the fill layer overlying the plurality of mesas until the polish-stop layer is exposed.