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Patent US5675279A successfully refreshed from Google Patents.
US5675279A
Expired / Lapsed
US
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Voltage stepup circuit for integrated semiconductor circuits
Assignee: Toshiba Corp
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Filing: 1996-06-20
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Granted: 1997-10-07
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Expires: 2016-06-20
Abstract
Abstract A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal. A first clock amplitude control circuit limits the amplitude of the first clock signal to be supplied to the first clock signal supply node to a predetermined level and applies the first amplitude-limited clock signal to the first clock signal supply node. A second clock amplitude control circuit limits the amplitude of the second clock signal to be supplied to the second clock signal supply node to a predetermined level and applies the second amplitude-limited clock signal to the second clock signal supply node.
Inventors
- 👤 Takuya Fujimoto
- 👤 Yoshiharu Hirata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:24
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H03; H03K; H03K17/00; H03K17/06; H03K17/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
307 words
A voltage stepup circuit, comprising: a plurality of stepup circuit units connected in series between an input voltage node receiving a supply voltage and an output voltage node, each stepup circuit unit comprising a first MOS and a second MOS transistor connected in series, each first and second MOS transistor having a drain and a gate connected together, each second MOS transistor having a source connected to the drain and gate of a first MOS transistor of a next series-connected stepup circuit unit, the source of the second MOS transistor of a last one of said plurality of stepup circuit units being connected to the output voltage node, and the drain and the gate of the first MOS-transistor of a first one of said plurality of stepup circuit units being connected to the input voltage node; a plurality of first stepup capacitors respectively connected between the drain and gate of the first MOS transistors of said plurality of stepup circuit units and a first clock signal supply node; a plurality of second stepup capacitors respectively connected between the drain and gate of the second MOS transistors of said plurality of stepup circuit units and a second clock signal supply node; first clock amplitude control circuit means for receiving a first clock signal, and for supplying a first amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the first clock signal supply node; and second clock amplitude control circuit means for receiving a second clock signal, and for supplying second amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the second clock signal supply node, said second amplitude-limited clock signal having a pulse width which does not overlap in time with that of the first amplitude-limited clock signal.
Claim 2
Dependent Claim
307 words
A voltage stepup circuit, comprising: a plurality of stepup circuit units connected in series between an input voltage node receiving a supply voltage and an output voltage node, each stepup circuit unit comprising a first MOS and a second MOS transistor connected in series, each first and second MOS transistor having a drain and a gate connected together, each second MOS transistor having a source connected to the drain and gate of a first MOS transistor of a next series-connected stepup circuit unit, the source of the second MOS transistor of a last one of said plurality of stepup circuit units being connected to the output voltage node, and the drain and the gate of the first MOS-transistor of a first one of said plurality of stepup circuit units being connected to the input voltage node; a plurality of first stepup capacitors respectively connected between the drain and gate of the first MOS transistors of said plurality of stepup circuit units and a first clock signal supply node; a plurality of second stepup capacitors respectively connected between the drain and gate of the second MOS transistors of said plurality of stepup circuit units and a second clock signal supply node; first clock amplitude control circuit means for receiving a first clock signal, and for supplying a first amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the first clock signal supply node; and second clock amplitude control circuit means for receiving a second clock signal, and for supplying second amplitude-limited clock signal amplitude-limited to a predetermined level regardless of variations in the level of the supply voltage to the second clock signal supply node, said second amplitude-limited clock signal having a pulse width which does not overlap in time with that of the first amplitude-limited clock signal.
Claim 3
Dependent Claim
145 words
A stepup circuit according to claim 1, wherein each of the first and second clock amplitude control circuit mean comprises: a third MOS transistor having one end connected to the input voltage node and a gate connected to ground potential; a fourth MOS transistor having one end connected to an other end of the third MOS transistor, a gate connected to receive a corresponding one of the first and second clock signals, and an other end connected to a corresponding one of the first and second clock signal supply nodes; and a fifth MOS transistor having one end connected to the other end of the fourth MOS transistor and to the corresponding one of the first and second clock signal supply nodes, a gate connected to receive the corresponding one of the first and second clock signals, and an other end connected to ground potential.
Claim 4
Dependent Claim
35 words
A stepup circuit according to claim 2, wherein the third MOS transistor is an N-channel depletion transistor, the fourth MOS transistor is a P-channel MOS transistor, and the fifth MOS transistor is an N-channel transistor.
Claim 5
Dependent Claim
169 words
A stepup circuit according to claim 1, wherein each of the first and second clock amplitude control circuit means comprises: a third MOS transistor having one end connected to the input voltage node; a fourth MOS transistor having one end connected to an other end of the third MOS transistor, a gate connected to receive a corresponding one of said first and second clock signals, and an other end connected to a corresponding one of the first and second clock signal supply nodes; a fifth MOS transistor having one connected to the other end of the fourth MOS transistor and to the corresponding one of the first and second clock signal supply nodes, a gate connected to receive the corresponding one of the first and second clock signals, and an other end connected to ground potential; and a sixth MOS transistor having one end connected to the input voltage node, a gate connected to ground potential, and an other end connected to the gate of the third MOS transistor.
Claim 6
Dependent Claim
39 words
A stepup circuit according to claim 4, wherein the third MOS transistor and the sixth MOS transistors are N-channel depletion transistors, the fourth MOS transistor is a P/channel MOS transistor, and the fifth MOS transistor is an N-channel transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |