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US5745407A
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Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
Assignee: California Institute of Technology
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Filing: 1996-04-05
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Granted: 1998-04-28
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Expires: 2016-04-05
Abstract
Abstract A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind, wherein the semiconducting devices of the first kind exhibit N-type negative differential resistance, and the semiconducting devices of the second kind may exhibit exponential or linear current-voltage characteristics.
Inventors
- 👤 Harold J. Levy
- 👤 Thomas C. McGill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; G11C11/56; H; H10; H10B; H10B63/00; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5614; Y; Y10; Y10S; Y10S438/00; Y10S438/979
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
358 words
A self-aligned, three-dimensional computer memory structure comprising: a plurality of first conducting regions arranged in C columns, each of the first conducting regions having a plurality of sides; a first array having a plurality of first semiconducting regions arranged in R rows and C columns, each of the first semiconductor regions having a plurality of sides, a first side of each of the first semiconducting regions in a column coupled to a first side of the first conducting region in the corresponding column; a second array having a plurality of second semiconducting regions arranged in R rows and C columns, each of the second semiconducting regions having a plurality of sides, a first side of each of the second semiconducting regions coupled to a second side of a corresponding one of the first semiconducting regions; and a plurality of second conducting regions arranged in R rows, each of the second conducting regions having a plurality of sides, a second side of each of the second semiconducting regions in a row coupled to a first side of the second conducting region in the corresponding row; wherein a second side and a third side of the first conducting region in each column are aligned to a third side and a fourth side of each of the first semiconducting regions in the corresponding column, respectively; the third side and the fourth side of each of the first semiconducting regions are aligned to a third side and a fourth side of a corresponding one of the second semiconducting regions, respectively; a fifth side and a sixth side of each of the first semiconducting regions are aligned to a fifth side and a sixth side of a corresponding one of the second semiconducting region, respectively; and the fifth side and the sixth side of each of the second semiconducting regions in a row are aligned to a second side and a third side of the second conducting region in the corresponding row, respectively; wherein the first semiconducting regions and the second semiconducting regions are transistorless devices and each of the first semiconducting regions comprises either of a switch diode or a load device.
Claim 2
Dependent Claim
358 words
A self-aligned, three-dimensional computer memory structure comprising: a plurality of first conducting regions arranged in C columns, each of the first conducting regions having a plurality of sides; a first array having a plurality of first semiconducting regions arranged in R rows and C columns, each of the first semiconductor regions having a plurality of sides, a first side of each of the first semiconducting regions in a column coupled to a first side of the first conducting region in the corresponding column; a second array having a plurality of second semiconducting regions arranged in R rows and C columns, each of the second semiconducting regions having a plurality of sides, a first side of each of the second semiconducting regions coupled to a second side of a corresponding one of the first semiconducting regions; and a plurality of second conducting regions arranged in R rows, each of the second conducting regions having a plurality of sides, a second side of each of the second semiconducting regions in a row coupled to a first side of the second conducting region in the corresponding row; wherein a second side and a third side of the first conducting region in each column are aligned to a third side and a fourth side of each of the first semiconducting regions in the corresponding column, respectively; the third side and the fourth side of each of the first semiconducting regions are aligned to a third side and a fourth side of a corresponding one of the second semiconducting regions, respectively; a fifth side and a sixth side of each of the first semiconducting regions are aligned to a fifth side and a sixth side of a corresponding one of the second semiconducting region, respectively; and the fifth side and the sixth side of each of the second semiconducting regions in a row are aligned to a second side and a third side of the second conducting region in the corresponding row, respectively; wherein the first semiconducting regions and the second semiconducting regions are transistorless devices and each of the first semiconducting regions comprises either of a switch diode or a load device.
Claim 3
Dependent Claim
41 words
The computer memory structure of claim 1 wherein isolation regions exist between the first conducting regions, isolation regions exist between the first semiconducting regions, isolation regions exist between the second semiconducting regions, and isolation regions exist between the second conducting regions.
Claim 4
Dependent Claim
45 words
The computer memory structure of claim 2 wherein the isolation regions between the first conducting regions, the isolation regions between the first semiconducting regions, the isolation regions between the second semiconducting regions and the isolation regions between the second conducting regions are filled with air.
Claim 5
Dependent Claim
47 words
The computer memory structure of claim 2 wherein the isolation regions between the first conducting regions, the isolation regions between the first semiconducting regions, the isolation regions between the second semiconducting regions and the isolation regions between the second conducting regions are filled with solid insulating materials.
Claim 6
Dependent Claim
89 words
The computer memory structure of claim 4 wherein each of the second semiconducting regions comprises either of a load device or a switch diode wherein the first semiconducting regions and the second semiconducting regions are different so that when each of the first semiconducting regions is one of the switch diodes, each of the second semiconducting regions is one of the load devices, and when each of the first semiconducting regions is one of the load devices, each of the second semiconducting regions is one of the switch diodes.
Claim 7
Dependent Claim
17 words
The computer memory structure of claim 5 wherein each of the switch diodes exhibits negative differential resistance.
Claim 8
Dependent Claim
25 words
The computer memory structure of claim 6 wherein each of the load devices exhibits either of an exponential current-voltage characteristic and a linear current-voltage characteristic.
Claim 9
Dependent Claim
49 words
The computer memory structure of claim 7 wherein each of the switch diodes exhibits negative differential resistance including a high-impedance region, a low-impedance region and a negative-resistance region, the negative differential resistance being characterized by a voltage-current relationship having multiple values of current for the same value of voltage.
Claim 10
Dependent Claim
90 words
The computer memory structure of claim 1 wherein each of the first conducting regions comprises either of a bit line and a word line, and each of the second conducting regions comprises either of a word line or a bit line wherein the first conducting regions and the second conducting regions are different so that when the first conducting regions include the word lines, the second conducting regions include the bit lines, and when the first conducting regions include the bit lines, the second conducting regions include the word lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |