US5765035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recorder buffer capable of detecting dependencies between accesses to a pair of caches
Assignee: GlobalFoundries Inc
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Filing: 1995-11-20
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Granted: 1998-06-09
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Expires: 2015-11-20
Abstract
Abstract A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage. The comparator circuits used to perform the comparison are configured to compare a field of address bits instead of the entire address, reducing the size while still maintaining accurate dependency checking by qualifying the resulting comparison signals with an indication that both addresses hit in the same storage location within the stack cache.
Inventors
- 👤 Thang M. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3861
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
237 words
A dependency checking structure for detecting dependencies between accesses to a pair of caches comprising a reorder buffer including: a request bus configured to convey an access address indicative of a first memory operand; a plurality of storage locations wherein each of said plurality of storage locations is configured to store information pertaining to an instruction including an address of a second memory operand; a plurality of comparator circuits wherein each of said plurality of comparator circuits is coupled to a respective one of said plurality of storage locations to receive said memory operand address, and wherein said each of said plurality of comparator circuits is coupled to said request bus, and wherein each of said plurality of comparator circuits is configured to produce a comparison signal indicative of equality between a field of said memory operand address and a corresponding field of said access address, wherein a field of an address excludes at least one hit of said address; and a control unit coupled to said plurality of storage locations and to said request bus, and further coupled to each of said plurality of comparator circuits to receive said comparison signal, wherein said control unit is configured to convey a dependency signal indicative of a dependency between said access address and said memory operand address according to said comparison signals, and wherein said control unit is configured to convey said dependency signal upon a dependency bus.
Claim 2
Dependent Claim
237 words
A dependency checking structure for detecting dependencies between accesses to a pair of caches comprising a reorder buffer including: a request bus configured to convey an access address indicative of a first memory operand; a plurality of storage locations wherein each of said plurality of storage locations is configured to store information pertaining to an instruction including an address of a second memory operand; a plurality of comparator circuits wherein each of said plurality of comparator circuits is coupled to a respective one of said plurality of storage locations to receive said memory operand address, and wherein said each of said plurality of comparator circuits is coupled to said request bus, and wherein each of said plurality of comparator circuits is configured to produce a comparison signal indicative of equality between a field of said memory operand address and a corresponding field of said access address, wherein a field of an address excludes at least one hit of said address; and a control unit coupled to said plurality of storage locations and to said request bus, and further coupled to each of said plurality of comparator circuits to receive said comparison signal, wherein said control unit is configured to convey a dependency signal indicative of a dependency between said access address and said memory operand address according to said comparison signals, and wherein said control unit is configured to convey said dependency signal upon a dependency bus.
Claim 3
Dependent Claim
76 words
The dependency checking structure as recited in claim 1 wherein said control unit is configured to indicate said dependency if said access address is associated with a second instruction subsequent to a first instruction associated with said memory operand address, and if said first instruction causes a write access to at least one of said pair of caches, and if said second instruction causes a read access to at least one of said pair of caches.
Claim 4
Dependent Claim
39 words
The dependency checking structure as recited in claim 2 further comprising a load/store unit coupled to said request bus and to said dependency bus wherein said load/store unit is configured to convey said access address upon said request bus.
Claim 5
Dependent Claim
36 words
The dependency checking structure as recited in claim 3 wherein said load/store unit is configured to receive said dependency signal and to stall said second instruction until said first instruction is retired by said reorder buffer.
Claim 6
Dependent Claim
88 words
The dependency checking structure as recited in claim 2 wherein said reorder buffer is configured to indicate said dependency if said access address is associated with a third instruction prior to a fourth instruction associated with said memory operand address and if said third instruction causes a write access to at least one of said pair of caches and if said fourth instruction causes a read access to at least one of said pair of caches, and wherein said dependency signal is further indicative of said fourth instruction.
Claim 7
Dependent Claim
39 words
The dependency checking structure as recited in claim 5 further comprising a load/store unit coupled to said request bus and to said dependency bus wherein said load/store unit is configured to convey said access address upon said request bus.
Claim 8
Dependent Claim
29 words
The dependency checking structure as recited in claim 6 wherein said load/store unit is configured to receive said dependency signal and to flush instructions subsequent to said fourth instruction.
Claim 9
Dependent Claim
37 words
The dependency checking structure as recited in claim 5 further comprising a plurality of reservation stations coupled to said dependency bus wherein said plurality of reservation stations are configured to store instructions prior to said instructions' execution.
Claim 10
Dependent Claim
31 words
The dependency checking structure as recited in claim 8 wherein said plurality of reservation stations are configured to receive said dependency signal and to flush instructions subsequent to said fourth instruction.
Claim 11
Dependent Claim
32 words
The dependency checking structure as recited in claim 5 further comprising a plurality of decode units coupled to said dependency bus wherein said plurality of decode units are configured to decode instructions.
Claim 12
Dependent Claim
31 words
The dependency checking structure as recited in claim 10 wherein said plurality of decode units are configured to receive said dependency signal and to flush instructions subsequent to said fourth instruction.
Claim 13
Dependent Claim
30 words
The dependency checking structure as recited in claim 1 wherein said field of said memory operand address and said corresponding field of said access address each comprise seven consecutive bits.
Claim 14
Dependent Claim
30 words
The dependency checking structure as recited in claim 1 wherein said field of said memory operand address and said corresponding field of said access address each comprise eight consecutive bits.
Claim 15
Dependent Claim
34 words
The dependency checking structure as recited in claim 1 wherein said access address is formed by an indirect addressing mode in which said access address is formed from a value stored in a register.
Claim 16
Dependent Claim
58 words
The dependency checking structure as recited in claim 1 wherein said field of said memory operand address and said corresponding field of said access address each comprise an index field, and wherein said index field identifies a cache line within one of said pair of caches corresponding to said memory operand address and to said access address, respectively.
Claim 17
Dependent Claim
45 words
The dependency checking structure as recited in claim 15 wherein said field of said memory operand address and said corresponding field of said access address each further comprise an offset field, and wherein said offset field identifies one or more bytes within said cache line.
Claim 18
Dependent Claim
73 words
The dependency checking structure as recited in claim 1 wherein said each of said plurality of storage locations is further configured to store an indication that said memory operand address hits in one of said pair of caches, and wherein said control unit is configured to convey said dependency signal according to said comparison signals and according to corresponding indications that said memory operand address hits in one of said pair of caches.
Claim 19
Dependent Claim
62 words
The dependency checking structure as recited in claim 1 wherein said each of said plurality of storage locations is further configured to store an indication of a way of said one of said pair of caches in which said memory operand address hits, and wherein said control unit is configured to convey said dependency signal according to corresponding indications of said way.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |