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US5825201A
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Programming architecture for a programmable integrated circuit employing antifuses
Assignee: QuickLogic Corp
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Filing: 1996-06-21
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Granted: 1998-10-20
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Expires: 2016-06-21
Abstract
Abstract A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed.
Inventors
- 👤 Paige A. Kolze
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; H03K17/00; H03K17/22; H03K17/223; H03K19/17736; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
342 words
A programmable integrated circuit, comprising: a logic module; a first programming conductor extending in a first dimension from a first programming driver; a second programming conductor extending in the first dimension from a second programming driver; a first programming transistor; a first wire segment extending from the logic module in a second dimension to a first electrode of the first programming transistor, a second electrode of the first programming transistor being coupled to the first programming conductor, the second dimension being perpendicular to the first dimension; a second programming transistor; a second wire segment extending from the logic module in the second dimension to a first electrode of the second programming transistor, a second electrode of the second programming transistor being coupled to the second programming conductor; a third programming transistor; a third wire segment extending from the logic module in the second dimension to a first electrode of the third programming transistor, a second electrode of the third programming transistor being coupled to the first programming conductor; a fourth programming transistor; a fourth wire segment extending from the logic module in the second dimension to a first electrode of the fourth programming transistor, a second electrode of the fourth programming transistor being coupled to the second programming conductor; a first programming control conductor being coupled to a gate electrode of the first programming transistor and to a gate electrode of the second programming transistor; a second programming control conductor being coupled to a gate electrode of the third programming transistor and to a gate electrode of the fourth programming transistor; a plurality of third wire segments extending parallel to one another in the first dimension, each of the third wire segments crossing the first, second, third and fourth wire segments; and a plurality of antifuses, one of the antifuses being disposed at each location where a third wire segment crosses one of the first, second, third or fourth wire segments wherein the number of programming conductors extending in the first dimension is substantially equal to the number of programming control conductors.
Claim 2
Dependent Claim
342 words
A programmable integrated circuit, comprising: a logic module; a first programming conductor extending in a first dimension from a first programming driver; a second programming conductor extending in the first dimension from a second programming driver; a first programming transistor; a first wire segment extending from the logic module in a second dimension to a first electrode of the first programming transistor, a second electrode of the first programming transistor being coupled to the first programming conductor, the second dimension being perpendicular to the first dimension; a second programming transistor; a second wire segment extending from the logic module in the second dimension to a first electrode of the second programming transistor, a second electrode of the second programming transistor being coupled to the second programming conductor; a third programming transistor; a third wire segment extending from the logic module in the second dimension to a first electrode of the third programming transistor, a second electrode of the third programming transistor being coupled to the first programming conductor; a fourth programming transistor; a fourth wire segment extending from the logic module in the second dimension to a first electrode of the fourth programming transistor, a second electrode of the fourth programming transistor being coupled to the second programming conductor; a first programming control conductor being coupled to a gate electrode of the first programming transistor and to a gate electrode of the second programming transistor; a second programming control conductor being coupled to a gate electrode of the third programming transistor and to a gate electrode of the fourth programming transistor; a plurality of third wire segments extending parallel to one another in the first dimension, each of the third wire segments crossing the first, second, third and fourth wire segments; and a plurality of antifuses, one of the antifuses being disposed at each location where a third wire segment crosses one of the first, second, third or fourth wire segments wherein the number of programming conductors extending in the first dimension is substantially equal to the number of programming control conductors.
Claim 3
Dependent Claim
110 words
The programmable integrated circuit of claim 1, wherein the first programming control conductor has a first portion which extends in the first dimension and couples to the gates of the first and second programming transistors, and wherein the first programming control conductor also has a second portion which extends in the second dimension and crosses the logic module, and wherein the second programming control conductor has a first portion which extends in the first dimension and couples to the gates of the third and fourth programming transistors, and wherein the second programming control conductor also has a second portion which extends in the second dimension and crosses the logic module.
Claim 4
Dependent Claim
39 words
The programmable integrated circuit of claim 1, further comprising a plurality of like logic modules disposed in a column extending in the first dimension, the first and second programming conductors extending in the first dimension parallel to the column.
Claim 5
Dependent Claim
28 words
The programmable integrated circuit of claim 1, wherein the first, second, third and fourth wire segments are coupled to inputs of digital logic elements in the logic module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |