Patent US5828600A successfully refreshed from Google Patents.
US5828600A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile semiconductor memory
Assignee: Emergence Memory Solutions LLC
•
Filing: 1996-10-30
•
Granted: 1998-10-27
•
Expires: 2016-10-30
Abstract
Abstract Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.
Inventors
- 👤 Masataka Kato
- 👤 Tetsuo Adachi
- 👤 Toshihiro Tanaka
- 👤 Toshio Sasaki
- 👤 Hitoshi Kume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10; G11C16/12; G11C16/14; G11C16/16; G11C16/34; G11C16/3418; G11C16/3427; G11C8/00; G11C8/08; H; H10; H10B; H10B41/00; H10B41/30; H10B41/35; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
481 words
A non-volatile semiconductor memory having an electrically programmable/erasable function, comprising a plurality of memory arrays each including a plurality of memory cells disposed in a matrix having rows and columns, first and second voltage generators, and a sense circuit including a plurality of latches provided for said memory arrays: wherein each of said memory cells is a one-transistor type memory cell essentially consisting of one MOSFET including a source region and a drain region disposed in a portion of a semiconductor substrate in a mutually spaced-apart relationship, a gate insulating film having a substantially uniform film thickness from the surface of said source region to the surface of said drain region, a floating gate electrode formed on said gate insulating film, and a control gate formed on said floating gate electrode through an intermediate insulating film; wherein said drain regions of said MOSFETs of a plurality of said memory cells on the same column are connected to one data line in each of said memory cell arrays; wherein said control gates of said MOSFETs of a plurality of said memory cells on the same row are connected to one word line in each of said memory cell arrays; wherein, when an electric programming operation is carried out to pull out charges accumulated at a floating gate of the MOSFET of a memory cell, a first voltage having a first polarity with respect to a potential of said portion of said semiconductor substrate as a reference is applied from said first voltage generator to the drain region of the MOSFET of any memory cell to be subjected to said electric programming operation and a second voltage having a second polarity different from said first polarity with respect to the potential of said portion of said semiconductor substrate as the reference is applied to said control gate of said memory cell whereby said programming operation is effected by use of tunnel mechanism; wherein, when an electric erasing operation is carried out to inject charges into a floating gate of the MOSFET of a memory cell, a third voltage having said first polarity with respect to said semiconductor substrate is applied from said second generator to the control gates of a plurality of MOSFETs of memory cells to be subjected to said electric erasing operation and the others of said electrodes are all kept at the same voltage as that of said portion of said semiconductor substrate whereby said erasing operation is effected by use of tunnel mechanism; wherein a number of said latches is equal to a number of memory cells having MOSFETs whose control gates are connected to one word line subjected to a simultaneous erasing operation; and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 2
Dependent Claim
481 words
A non-volatile semiconductor memory having an electrically programmable/erasable function, comprising a plurality of memory arrays each including a plurality of memory cells disposed in a matrix having rows and columns, first and second voltage generators, and a sense circuit including a plurality of latches provided for said memory arrays: wherein each of said memory cells is a one-transistor type memory cell essentially consisting of one MOSFET including a source region and a drain region disposed in a portion of a semiconductor substrate in a mutually spaced-apart relationship, a gate insulating film having a substantially uniform film thickness from the surface of said source region to the surface of said drain region, a floating gate electrode formed on said gate insulating film, and a control gate formed on said floating gate electrode through an intermediate insulating film; wherein said drain regions of said MOSFETs of a plurality of said memory cells on the same column are connected to one data line in each of said memory cell arrays; wherein said control gates of said MOSFETs of a plurality of said memory cells on the same row are connected to one word line in each of said memory cell arrays; wherein, when an electric programming operation is carried out to pull out charges accumulated at a floating gate of the MOSFET of a memory cell, a first voltage having a first polarity with respect to a potential of said portion of said semiconductor substrate as a reference is applied from said first voltage generator to the drain region of the MOSFET of any memory cell to be subjected to said electric programming operation and a second voltage having a second polarity different from said first polarity with respect to the potential of said portion of said semiconductor substrate as the reference is applied to said control gate of said memory cell whereby said programming operation is effected by use of tunnel mechanism; wherein, when an electric erasing operation is carried out to inject charges into a floating gate of the MOSFET of a memory cell, a third voltage having said first polarity with respect to said semiconductor substrate is applied from said second generator to the control gates of a plurality of MOSFETs of memory cells to be subjected to said electric erasing operation and the others of said electrodes are all kept at the same voltage as that of said portion of said semiconductor substrate whereby said erasing operation is effected by use of tunnel mechanism; wherein a number of said latches is equal to a number of memory cells having MOSFETs whose control gates are connected to one word line subjected to a simultaneous erasing operation; and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 3
Dependent Claim
283 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a decoder which selects a word line coupled with memory cells storing data to be erased from said plurality of word lines, and which supplies an erase voltage to said word line coupled with memory cells storing data to be erased, wherein data of memory cells coupled to a word line supplied with said erase voltage are erased by use of tunnel mechanism; and a plurality of data latch circuits which latch data to be written in erased memory cells; wherein a number of said plurality of data latch circuits is equal that of said erased memory cells, the data writing being effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 4
Dependent Claim
283 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a decoder which selects a word line coupled with memory cells storing data to be erased from said plurality of word lines, and which supplies an erase voltage to said word line coupled with memory cells storing data to be erased, wherein data of memory cells coupled to a word line supplied with said erase voltage are erased by use of tunnel mechanism; and a plurality of data latch circuits which latch data to be written in erased memory cells; wherein a number of said plurality of data latch circuits is equal that of said erased memory cells, the data writing being effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 5
Dependent Claim
31 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 2, wherein data of memory cells corresponding to an address to be written with data are erased.
Claim 6
Dependent Claim
42 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 3, wherein said decoder selects a word line from said plurality of word lines in accordance with an address signal supplied from outside of said nonvolatile semiconductor memory.
Claim 7
Dependent Claim
31 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 4, wherein data latched in said plurality of data latch circuits are written in erased memory cells.
Claim 8
Dependent Claim
58 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 5, further comprising: a high voltage generator generating a high voltage when data of ones of said plurality of memory cells are erased, and a negative voltage generator generating a negative voltage when data are written in ones of said plurality of memory cells.
Claim 9
Dependent Claim
50 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 6, wherein said decoder is coupled with said high voltage generator and with said negative voltage generator, and wherein said decoder supplies one of said high voltage and said negative voltage to a selected word line.
Claim 10
Dependent Claim
264 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a decoder selecting memory cells to be written with data from said plurality of memory cells in accordance with an address signal; and a high voltage generator generating a high voltage; wherein said high voltage is supplied to memory cells selected in accordance with said address signal before data are written in said memory cells selected in accordance with said address signal and data of memory cells supplied with said high voltage are erased, the data writing and the data erasure being both effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 11
Dependent Claim
264 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a decoder selecting memory cells to be written with data from said plurality of memory cells in accordance with an address signal; and a high voltage generator generating a high voltage; wherein said high voltage is supplied to memory cells selected in accordance with said address signal before data are written in said memory cells selected in accordance with said address signal and data of memory cells supplied with said high voltage are erased, the data writing and the data erasure being both effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 12
Dependent Claim
40 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 8, further comprising: a plurality of word lines, each of which is coupled with corresponding ones of said plurality of memory cells, coupled to said decoder.
Claim 13
Dependent Claim
36 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 9, wherein said high voltage is supplied to ones of said plurality of memory cells through selected word lines by said decoder.
Claim 14
Dependent Claim
45 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 10, further comprising: a plurality of data latch circuits latching data to be written in ones of said plurality of memory cells coupled to a selected word line by said decoder.
Claim 15
Dependent Claim
29 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 11, further comprising: a negative voltage generator, generating a negative voltage, coupled to said decoder.
Claim 16
Dependent Claim
49 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 12, wherein said negative voltage is supplied to a selected word line by said decoder when data latched in said plurality of data latch circuits are written in ones of said plurality of memory cells.
Claim 17
Dependent Claim
36 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 13, wherein a number of said plurality of data latch circuits is equal to a number of memory cells to be erased.
Claim 18
Dependent Claim
328 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a plurality of data latch circuits which latch data to be written in ones of said plurality of memory cells; and a decoder which selects a word line coupled with memory cells to be written with data latched in said plurality of latch circuits from said plurality of word lines, which supplies an erase voltage and a write voltage to a selected word line; wherein data of memory cells coupled to said selected word line are erased by being supplied with said erase voltage to said selected word line, wherein data latched in said plurality of data latch circuits are written in said memory cells coupled to said selected word lines by being supplied with said negative voltage to said selected word line after said data of said memory cells coupled to said selected word line are erased, the data writing and the data erasing being both effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 19
Dependent Claim
328 words
A non-volatile semiconductor memory having an electrically programmable and erasable function comprising: a plurality of memory cells each of which is a one-transistor type memory cell essentially consisting of one MOSFET which comprises: a first and a second region formed in a semiconductor body, a first insulating film covering at least a channel forming region between the first and the second region at a surface of the semiconductor body, a floating gate covering the first insulating film at least between the first and the second region, a second insulating film covering the floating gate at least between the first and the second region, and a control gate, covering the second insulating film at least between the first and the second region; a plurality of word lines each of which is coupled with corresponding ones of said plurality of memory cells; a plurality of data latch circuits which latch data to be written in ones of said plurality of memory cells; and a decoder which selects a word line coupled with memory cells to be written with data latched in said plurality of latch circuits from said plurality of word lines, which supplies an erase voltage and a write voltage to a selected word line; wherein data of memory cells coupled to said selected word line are erased by being supplied with said erase voltage to said selected word line, wherein data latched in said plurality of data latch circuits are written in said memory cells coupled to said selected word lines by being supplied with said negative voltage to said selected word line after said data of said memory cells coupled to said selected word line are erased, the data writing and the data erasing being both effected by use of tunnel mechanism, and wherein a number of memory cells connected to one word line is the same as a number of memory cells to be simultaneously erased and a number of memory cells to be simultaneously written.
Claim 20
Dependent Claim
34 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 15, wherein a number of said plurality of data latch circuits is equal to that of said erased memory cells.
Claim 21
Dependent Claim
31 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 16, wherein data of memory cells corresponding to an address to be written with data are erased.
Claim 22
Dependent Claim
43 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 17, wherein said decoder selects a word line from said plurality of word lines in accordance with an address signal supplied from outside of said non volatile semiconductor memory.
Claim 23
Dependent Claim
31 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 18, wherein data latched in said plurality of data latch circuits are written in erased memory cells.
Claim 24
Dependent Claim
58 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 19, further comprising: a high voltage generator generating said erase voltage when data of ones of said plurality of memory cells are erased; and a negative voltage generator generating said write voltage when data are written in ones of said plurality of memory cells.
Claim 25
Dependent Claim
31 words
The non-volatile semiconductor memory having an electrically programmable and erasable function according to claim 20, wherein said decoder is coupled with said high voltage generator and with said negative voltage generator.
Claim 26
Dependent Claim
53 words
The non-volatile semiconductor memory according to claim 1, further comprising data lines each constituting one of said columns; and common source lines one provided for each of said data lines, the source regions of the one-transistor type memory cells on each column are coupled to an associated one of said common source lines.
Claim 27
Dependent Claim
53 words
The non-volatile semiconductor memory according to claim 2, further comprising data lines each constituting one of said columns; and common source lines one provided for each of said data lines, the source regions of the one-transistor type memory cells on each column are coupled to an associated one of said common source lines.
Claim 28
Dependent Claim
53 words
The non-volatile semiconductor memory according to claim 8, further comprising data lines each constituting one of said columns; and common source lines one provided for each of said data lines, the source regions of the one-transistor type memory cells on each column are coupled to an associated one of said common source lines.
Claim 29
Dependent Claim
53 words
The non-volatile semiconductor memory according to claim 15, further comprising data lines each constituting one of said columns; and common source lines one provided for each of said data lines, the source regions of the one-transistor type memory cells on each column are coupled to an associated one of said common source lines.
Claim 30
Dependent Claim
34 words
A non-volatile semiconductor memory according to claim 1, wherein all memory cells of a row coupled to a word line constitute a unit of memory cells which can be simultaneously erased or simultaneously written.
Claim 31
Dependent Claim
34 words
A non-volatile semiconductor memory according to claim 2, wherein all memory cells of a row coupled to a word line constitute a unit of memory cells which can be simultaneously erased or simultaneously written.
Claim 32
Dependent Claim
34 words
A non-volatile semiconductor memory according to claim 8, wherein all memory cells of a row coupled to a word line constitute a unit of memory cells which can be simultaneously erased or simultaneously written.
Claim 33
Dependent Claim
34 words
A non-volatile semiconductor memory according to claim 15, wherein all memory cells of a row coupled to a word line constitute a unit of memory cells which can be simultaneously erased or simultaneously written.
References Cited (Backward Citations)
JPS62276878A
Cited
US4924437A
Cited
US5168335A
Cited
US5053648A
Cited
US5060195A
Cited
JPH03219496A
Cited
JPH0414871A
Cited
US5222040A
Cited
US5363330A
Cited
US5392253A
Cited
US5396459A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |