Patent US5835441A successfully refreshed from Google Patents.
US5835441A
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Column select latch for SDRAM
Assignee: Micron Technology Inc
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Filing: 1997-08-21
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Granted: 1998-11-10
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Expires: 2017-08-21
Abstract
Abstract A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.
Inventors
- 👤 Mirmajid Seyyedy
- 👤 Jeffrey P. Wright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:58
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C7/1072; G11C7/12
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
101 words
A synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns; address inputs for receiving a plurality of address signals; a column decode circuit for decoding the plurality of address inputs and producing an output signal identifying a column of the memory array; a latch circuit coupled to the column decode circuit for latching the output signal; and a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit electrically isolating the latch circuit from the column select circuit in response to an enable signal.
Claim 2
Dependent Claim
101 words
A synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns; address inputs for receiving a plurality of address signals; a column decode circuit for decoding the plurality of address inputs and producing an output signal identifying a column of the memory array; a latch circuit coupled to the column decode circuit for latching the output signal; and a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit electrically isolating the latch circuit from the column select circuit in response to an enable signal.
Claim 3
Dependent Claim
31 words
The synchronous memory device of claim 1 wherein the coupling circuit comprises a logic circuit for receiving the output signal and the enable signal and producing a column select output signal.
Claim 4
Dependent Claim
16 words
The synchronous memory device of claim 2 wherein the logic circuit is a logical AND gate.
Claim 5
Dependent Claim
42 words
The synchronous memory device of claim 1 further comprising an isolation device electrically located between the column decode circuit and the latch circuit, the isolation device electrically isolating the latch from the column decode circuit in response to a latch isolation signal.
Claim 6
Dependent Claim
140 words
A synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns; address inputs for receiving a plurality of address signals; a first column decode circuit for decoding some of the plurality of address inputs and producing a first output signal; a latch circuit coupled to the first column decode circuit for latching the first output signal; a second column decode circuit for decoding some of the plurality of address inputs; an enable circuit coupled to the second column decode circuit and adapted to receive an enable signal, the enable circuit producing a second output signal; and a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit electrically isolating the latch circuit from the column select circuit in response to the second output signal.
Claim 7
Dependent Claim
140 words
A synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns; address inputs for receiving a plurality of address signals; a first column decode circuit for decoding some of the plurality of address inputs and producing a first output signal; a latch circuit coupled to the first column decode circuit for latching the first output signal; a second column decode circuit for decoding some of the plurality of address inputs; an enable circuit coupled to the second column decode circuit and adapted to receive an enable signal, the enable circuit producing a second output signal; and a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit electrically isolating the latch circuit from the column select circuit in response to the second output signal.
Claim 8
Dependent Claim
44 words
The synchronous memory device of claim 5 further comprising an isolation device electrically located between the first column decode circuit and the latch circuit, the isolation device electrically isolating the latch from the first column decode circuit in response to a latch isolation signal.
Claim 9
Dependent Claim
30 words
The synchronous memory device of claim 5 wherein the coupling circuit comprises a logic circuit for receiving the first and second output signals and producing a column select output signal.
Claim 10
Dependent Claim
16 words
The synchronous memory device of claim 7 wherein the logic circuit is a logical AND gate.
Claim 11
Dependent Claim
34 words
The synchronous memory device of claim 5 wherein the enable circuit comprises a logic circuit coupled to the second column decode circuit and the enable signal, the logic circuit producing a second output signal.
Claim 12
Dependent Claim
16 words
The synchronous memory device of claim 9 wherein the logic circuit comprises a logical AND gate.
Claim 13
Dependent Claim
233 words
A data storage system comprising: a microprocessor; and a synchronous memory device connected to the microprocessor, the synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns, address inputs connected to the microprocessor for receiving a plurality of address signals, a first column decode circuit for decoding some of the plurality of address inputs and producing a first output signal, a latch circuit coupled to the first column decode circuit for latching the first output signal, a second column decode circuit for decoding some of the plurality of address inputs, an enable circuit coupled to the second column decode circuit and adapted to receive an enable signal, the enable circuit comprises a logic circuit coupled to the second column decode circuit and the enable signal, the logic circuit producing a second output signal, a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit comprises a logic circuit for receiving the first and second output signals and producing a column select output signal to electrically isolate the latch circuit from the column select circuit in response to the second output signal, and an isolation device electrically located between the first column decode circuit and the latch circuit, the isolation device electrically isolating the latch from the first column decode circuit in response to a latch isolation signal.
Claim 14
Dependent Claim
233 words
A data storage system comprising: a microprocessor; and a synchronous memory device connected to the microprocessor, the synchronous memory device comprising: a memory array of memory cells, the memory cells being arranged in addressable rows and columns, address inputs connected to the microprocessor for receiving a plurality of address signals, a first column decode circuit for decoding some of the plurality of address inputs and producing a first output signal, a latch circuit coupled to the first column decode circuit for latching the first output signal, a second column decode circuit for decoding some of the plurality of address inputs, an enable circuit coupled to the second column decode circuit and adapted to receive an enable signal, the enable circuit comprises a logic circuit coupled to the second column decode circuit and the enable signal, the logic circuit producing a second output signal, a coupling circuit electrically located between the latch circuit and a column select circuit, the coupling circuit comprises a logic circuit for receiving the first and second output signals and producing a column select output signal to electrically isolate the latch circuit from the column select circuit in response to the second output signal, and an isolation device electrically located between the first column decode circuit and the latch circuit, the isolation device electrically isolating the latch from the first column decode circuit in response to a latch isolation signal.
Claim 15
Independent Claim
93 words
A method of selecting a column of memory cells in a synchronous memory device, the method comprising the steps of: receiving a plurality of address signals on address input lines; decoding the plurality of address signals using decode circuitry to identify a column of memory cells; producing an output signal identifying the column of memory cells in response to the decoded plurality of address signals; latching the output signal; and producing a column select signal in response to a coupling circuit which operates in response to an enable signal and the output signal.
Claim 16
Independent Claim
93 words
A method of selecting a column of memory cells in a synchronous memory device, the method comprising the steps of: receiving a plurality of address signals on address input lines; decoding the plurality of address signals using decode circuitry to identify a column of memory cells; producing an output signal identifying the column of memory cells in response to the decoded plurality of address signals; latching the output signal; and producing a column select signal in response to a coupling circuit which operates in response to an enable signal and the output signal.
Claim 17
Dependent Claim
48 words
The method of claim 12 further comprising the steps of: electrically isolating the latched output signal from the decode circuitry; receiving a second plurality of address signals on the address input lines; and decoding the second plurality of address signals to identify a second column of memory cells.
Claim 18
Independent Claim
101 words
A method of selecting a column of memory cells in a synchronous memory device, the method comprising the steps of: receiving a plurality of address signals on address input lines; decoding some of the plurality of address signals using first decode circuitry to produce a first decoded signal; decoding additional ones of the plurality of address signals using second decode circuitry to produce a second decoded signal; latching the first decoded signal; and producing a column select signal in response to a coupling circuit which operates in response to the first decoded signal, the second decoded signal, and an enable signal.
Claim 19
Independent Claim
101 words
A method of selecting a column of memory cells in a synchronous memory device, the method comprising the steps of: receiving a plurality of address signals on address input lines; decoding some of the plurality of address signals using first decode circuitry to produce a first decoded signal; decoding additional ones of the plurality of address signals using second decode circuitry to produce a second decoded signal; latching the first decoded signal; and producing a column select signal in response to a coupling circuit which operates in response to the first decoded signal, the second decoded signal, and an enable signal.
Claim 20
Dependent Claim
22 words
The method of claim 14 further comprising the steps of: electrically isolating the latched first decoded signal from the first decode circuitry.
Claim 21
Dependent Claim
15 words
The method of claim 14 further comprising the step of latching the second decoded signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |