Patent US5912845A successfully refreshed from Google Patents.
US5912845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit for substrate current induced hot e- injection (SCIHE) approach for VT convergence at low VCC voltage
Assignee: Macronix International Co Ltd
•
Filing: 1997-09-10
•
Granted: 1999-06-15
•
Expires: 2017-09-10
Abstract
Abstract A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
Inventors
- 👤 Chia-Shing Chen
- 👤 Mam-Tsung Wang
- 👤 Wenpin Lu
- 👤 Ming-Hung Chou
- 👤 Ying-Che Lo
- 👤 Ming-Shang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:05
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/107; G11C16/34; G11C16/3404; G11C16/3409; G11C16/3436; G11C16/344; G11C16/3445
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
82 words
A method for correcting an over-erase condition within a non-volatile memory array, comprising: providing a non-volatile memory array having a plurality of single transistor memory cells, each memory cell comprising a stacked pair of control and floating gates spaced above a channel region interposed between a source and drain region; and applying a first voltage to the control gate, an active current limiter to the source region, a non-positive voltage to the channel region, and a positive voltage to the drain region.
Claim 2
Independent Claim
82 words
A method for correcting an over-erase condition within a non-volatile memory array, comprising: providing a non-volatile memory array having a plurality of single transistor memory cells, each memory cell comprising a stacked pair of control and floating gates spaced above a channel region interposed between a source and drain region; and applying a first voltage to the control gate, an active current limiter to the source region, a non-positive voltage to the channel region, and a positive voltage to the drain region.
Claim 3
Dependent Claim
34 words
The method as recited in claim 1, wherein said providing step comprises patterning the stacked pair of control and floating gates from a stacked pair of polysilicon layers having a dielectric layer interposed therebetween.
Claim 4
Dependent Claim
30 words
The method as recited in claim 1, wherein said channel region comprises a portion of a single crystalline substrate material, wherein said portion is adapted to receive a non-positive voltage.
Claim 5
Dependent Claim
21 words
The method as recited in claim 1, wherein said non-positive voltage is a voltage having an absolute magnitude greater than 0.5.
Claim 6
Dependent Claim
21 words
The method as recited in claim 1, wherein said non-positive voltage is a voltage having an absolute magnitude greater than 1.
Claim 7
Dependent Claim
21 words
The method as recited in claim 1, wherein said positive voltage is a voltage having an absolute magnitude less than 5.
Claim 8
Dependent Claim
21 words
The method as recited in claim 1, wherein said positive voltage is a voltage having an absolute magnitude less than 4.5.
Claim 9
Dependent Claim
18 words
The method as recited in claim 1, wherein said first voltage is between -1 V and 6 V.
Claim 10
Dependent Claim
16 words
The method as recited in claim 1, wherein the active current limiter is a current mirror.
Claim 11
Dependent Claim
19 words
The method as recited in claim 1, wherein the active current limiter is an NMOSFET operating at saturation mode.
Claim 12
Dependent Claim
16 words
The method as recited in claim 1, wherein the active current limiter is a current source.
Claim 13
Dependent Claim
28 words
The method as recited in claim 1, wherein the active current limiter provides current in a range of 1.5 mA to 1.2 mA per 512 K memory cells.
Claim 14
Dependent Claim
25 words
The method as recited in claim 1, as a result of said applying step, inducing electrons onto said floating gate for neutralizing positive charge thereon.
References Cited (Backward Citations)
US4875188A
Cited
US5042009A
Cited
US5258949A
Cited
US5554868A
Cited
US5233562A
Cited
US5399891A
Cited
US5406521A
Cited
US5414664A
Cited
US5349220A
Cited
US5596530A
Cited
US5615153A
Cited
US5467306A
Cited
US5508959A
Cited
US5416738A
Cited
US5487033A
Cited
US5561620A
Cited
US5546340A
Cited
US5657271A
Cited
US5642311A
Cited
US5745410A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |