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US5915262A
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Cache system and method using tagged cache lines for matching cache strategy to I/O application
Assignee: GlobalFoundries Inc
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Filing: 1996-07-22
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Granted: 1999-06-22
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Expires: 2016-07-22
Abstract
Abstract A computer system including a processor, a main memory and a cache memory uses tagging of various regions of memory to define and select caching properties of transfers between the processor and memory via the cache. The main memory contains not only standard random access memory (RAM) and read-only memory (ROM) but also memory-mapped input/output (I/O) sources. Tagging of the memory regions configures the regions for association with a particular set of caching properties. For example, a memory-mapped video I/O buffer may be tagged with a MM -- IO -- VBUF tag designating the caching properties of write-back cacheability with weak read/write ordering. Low-level operating system software, such as the Hardware Abstraction Language (HAL) interface of the Windows NT™ operating system or device driver software, initialize the memory regions, the cache and make symbolic associations between the memory regions and the cache. The cache, operating as directed by the memory tags, allows read and write operations that are used for performing various types of multimedia or signal processing operations including decompression, drawing operations, compression, mixing, and the like, which are performed on a virtually-cached multimedia drawing surface. The data for performing the multimedia or signal processing operations are either already located on the I/O surface or read from another storage location local to the processor or from an external processor, which is also cached and tagged as a special cached region. The processor executes operations acting on the cached data. When all operations are completely executed by the processor, only the cached memory regions are flushed using a flush instruction such as CFLSH MM -- IO -- VBUF!. The flush instruction directs the cache to write back and invalidate the regions having the designated tag, here MM -- IO -- VBUF.
Inventors
- 👤 K. Vincent Bridgers
- 👤 Michael Drake
- 👤 Richard W. Schuckle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F2212/00; G06F2212/20; G06F2212/206
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
137 words
A computing apparatus comprising: a processor; a cache coupled to the processor; a bus coupled to the cache; a plurality of variable-characteristic memory regions external to the cache and coupled to the cache via the bus, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions, the memory region tags independently tagging cache characteristics of the plurality of memory regions according to a character of data in the variable-characteristic memory regions; a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 2
Dependent Claim
137 words
A computing apparatus comprising: a processor; a cache coupled to the processor; a bus coupled to the cache; a plurality of variable-characteristic memory regions external to the cache and coupled to the cache via the bus, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions, the memory region tags independently tagging cache characteristics of the plurality of memory regions according to a character of data in the variable-characteristic memory regions; a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 3
Dependent Claim
36 words
A computing apparatus according to claim 1 further comprising: an operating system executable on the processor and including a routine configuring the cache to the cache characteristics of a selected memory region including configuring symbolic associations.
Claim 4
Dependent Claim
27 words
A computing apparatus according to claim 2 wherein: the operating system includes a hardware abstraction level of a Windows NT™ operating system including the cache configuring routine.
Claim 5
Dependent Claim
20 words
A computing apparatus according to claim 2 wherein: the operating system includes a device driver including the cache configuring routine.
Claim 6
Dependent Claim
31 words
A computing apparatus according to claim 1 further comprising: a memory-mapped video I/O buffer coupled to the bus and having an address mapped to one of the plurality of memory regions.
Claim 7
Dependent Claim
37 words
A computing apparatus according to claim 5 wherein: the memory-mapped video I/O buffer has an associated memory region tag that tags the memory-mapped video I/O buffer with a cache characteristic of writeback cacheable with weak read-write ordering.
Claim 8
Dependent Claim
28 words
A computing apparatus according to claim 1 further comprising: a memory region tag of the plurality of memory region tags allocating a memory region to a cache line.
Claim 9
Dependent Claim
30 words
A computing apparatus according to claim 1 further comprising: a memory region tag of the plurality of memory region tags configuring a cache replacement strategy to a selected memory region.
Claim 10
Dependent Claim
35 words
A computing apparatus according to claim 1 further comprising: a memory region tag of the plurality of memory region tags configuring a cache line size to a cache line allocated to a selected memory region.
Claim 11
Dependent Claim
50 words
A computing apparatus according to claim 1 wherein: the memory region tags independently tag cache characteristics of the plurality of memory regions according to a character of data in the variable-characteristic memory regions including data locality, volume and timing of data transmission, and type of processing performed on the data.
Claim 12
Independent Claim
193 words
A method of operating a computing apparatus including a processor, a cache couple to the processor, a bus coupled to the cache, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache via the bus, and a tag memory, the method comprising: independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a characteristics of data of the plurality of variable-characteristic memory regions, the data having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor; and configuring the cache as directed by the tagging of the selected memory region; tagging a selected memory region of the plurality of memory regions to configure a cache line to include a plurality of storage locations for holding filter coefficients continuously while other storage in the cache line is periodically replaced; and configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 13
Independent Claim
193 words
A method of operating a computing apparatus including a processor, a cache couple to the processor, a bus coupled to the cache, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache via the bus, and a tag memory, the method comprising: independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a characteristics of data of the plurality of variable-characteristic memory regions, the data having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor; and configuring the cache as directed by the tagging of the selected memory region; tagging a selected memory region of the plurality of memory regions to configure a cache line to include a plurality of storage locations for holding filter coefficients continuously while other storage in the cache line is periodically replaced; and configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 14
Dependent Claim
55 words
A method according to claim 11 wherein the computing apparatus further includes a memory-mapped video I/O buffer coupled to the bus and having an address mapped to one of the plurality of memory regions, the method further comprising: tagging the memory-mapped video I/O buffer with a cache characteristic of writeback cacheable with weak read-write ordering.
Claim 15
Dependent Claim
37 words
A method according to claim 11 further comprising: tagging a selected memory region of the plurality of memory regions to allocate a memory region to a cache line; and allocating a memory region to a cache line.
Claim 16
Dependent Claim
41 words
A method according to claim 11 further comprising: tagging a selected memory region of the plurality of memory regions to configure a cache replacement strategy to a selected memory region; and configuring a cache replacement strategy to a selected memory region.
Claim 17
Dependent Claim
51 words
A method according to claim 11 further comprising: tagging a selected memory region of the plurality of memory regions to configure a cache line size to a cache line allocated to a selected memory region; and configuring a cache line size to a cache line allocated to a selected memory region.
Claim 18
Dependent Claim
191 words
A software computer program comprising a plurality of executable routines executing a method of operating a computing apparatus including a processor, a cache coupled to the processor, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache, and a tag memory, the method comprising: providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions; independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a character of data of the plurality of variable-characteristic memory regions, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor, and configuring the cache as directed by the tagging of the selected memory region; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 19
Dependent Claim
191 words
A software computer program comprising a plurality of executable routines executing a method of operating a computing apparatus including a processor, a cache coupled to the processor, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache, and a tag memory, the method comprising: providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions; independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a character of data of the plurality of variable-characteristic memory regions, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor, and configuring the cache as directed by the tagging of the selected memory region; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 20
Dependent Claim
202 words
A computer program product comprising a computer usable medium having computable readable code embodied therein including a plurality of executable routines executing a method of operating a computing apparatus including a processor, a cache coupled to the processor, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache, and a tag memory, the method comprising: providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions; independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a character of data of the plurality of variable-characteristic memory regions, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor; and configuring the cache as directed by the tagging of the selected memory region; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 21
Dependent Claim
202 words
A computer program product comprising a computer usable medium having computable readable code embodied therein including a plurality of executable routines executing a method of operating a computing apparatus including a processor, a cache coupled to the processor, a plurality of variable-characteristic memory regions external to the cache and coupled to the cache, and a tag memory, the method comprising: providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions; independently tagging ones of the plurality of variable-characteristic memory regions in the tag memory to define cache characteristics according to a character of data of the plurality of variable-characteristic memory regions, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; selecting a memory region of the plurality of variable-characteristic memory regions for supplying information for execution by the processor; and configuring the cache as directed by the tagging of the selected memory region; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 22
Independent Claim
142 words
A method of providing a computing apparatus comprising: providing a processor; providing a cache coupled to the processor; providing a bus coupled to the cache; providing a plurality of variable-characteristic memory regions coupled to the cache via the bus, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions, the memory region tags independently tagging cache characteristics of the plurality of memory regions according to a character of data in the variable-characteristic memory regions; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 23
Independent Claim
142 words
A method of providing a computing apparatus comprising: providing a processor; providing a cache coupled to the processor; providing a bus coupled to the cache; providing a plurality of variable-characteristic memory regions coupled to the cache via the bus, the variable-characteristic memory regions having variable data characteristics selected from among data flow rates, data volumes, and data processing characteristics; providing a tag memory including a plurality of memory region tags associated to ones of the plurality of variable-characteristic memory regions, the memory region tags independently tagging cache characteristics of the plurality of memory regions according to a character of data in the variable-characteristic memory regions; providing a memory region tag of the plurality of memory region tags configuring a cache line to include a plurality of storage locations holding filter coefficients continuously while other storage in the cache line is periodically replaced.
Claim 24
Dependent Claim
36 words
A method according to claim 18 further comprising: providing an operating system executable on the processor and including a routine configuring the cache to the cache characteristics of a selected memory region including configuring symbolic associations.
Claim 25
Dependent Claim
26 words
A method according to claim 19 wherein: the operating system includes a hardware abstraction level of a Windows NT™ operating system including the cache configuring routine.
Claim 26
Dependent Claim
19 words
A method according to claim 19 wherein: the operating system includes a device driver including the cache configuring routine.
Claim 27
Dependent Claim
32 words
A method according to claim 18 further comprising: providing a memory-mapped video I/O buffer coupled to the bus and having an address mapped to one of the plurality of variable-characteristic memory regions.
Claim 28
Dependent Claim
36 words
A method according to claim 22 wherein: the memory-mapped video I/O buffer has an associated memory region tag that tags the memory-mapped video I/O buffer with a cache characteristic of writeback cacheable with weak read-write ordering.
Claim 29
Dependent Claim
28 words
A method according to claim 18 further comprising: providing a memory region tag of the plurality of memory region tags allocating a memory region to a cache line.
Claim 30
Dependent Claim
30 words
A method according to claim 18 further comprising: providing a memory region tag of the plurality of memory region tags configuring a cache replacement strategy to a selected memory region.
Claim 31
Dependent Claim
35 words
A method according to claim 18 further comprising: providing a memory region tag of the plurality of memory region tags configuring a cache line size to a cache line allocated to a selected memory region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |