US5933386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Driving memory bitlines using boosted voltage
Assignee: Mitsubishi Electric US Inc
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Filing: 1997-12-23
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Granted: 1999-08-03
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Expires: 2017-12-23
Abstract
Abstract An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.
Inventors
- 👤 Robert Walker
- 👤 Stephen Camacho
- 👤 Tim Lao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C5/00; G11C5/14; G11C5/145; G11C7/12
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
114 words
An apparatus for driving a bitline driver of a memory device, comprising: a first write data line for carrying a data bit to be supplied to said bitline driver; a source of a boosted voltage larger in magnitude than an operating voltage; and a driving circuit coupled to said first write data line and said boosted voltage source for driving said data bit to said bitline driver at a level of said boosted voltage, said driving circuit including a level shifter having a voltage supplying circuit coupled to a write enable line for supplying said boosted voltage to said bitline driver when said write enable line and said first write data line are asserted.
Claim 2
Independent Claim
114 words
An apparatus for driving a bitline driver of a memory device, comprising: a first write data line for carrying a data bit to be supplied to said bitline driver; a source of a boosted voltage larger in magnitude than an operating voltage; and a driving circuit coupled to said first write data line and said boosted voltage source for driving said data bit to said bitline driver at a level of said boosted voltage, said driving circuit including a level shifter having a voltage supplying circuit coupled to a write enable line for supplying said boosted voltage to said bitline driver when said write enable line and said first write data line are asserted.
Claim 3
Dependent Claim
84 words
The apparatus recited in claim 1, wherein said level shifter comprises: a first transistor coupled to said first write data line; a second transistor coupled to said write enable line and to said first transistor; a third transistor coupled to said boost voltage and to said second transistor; and wherein when said first write data line and said write enable line are asserted, said first, second and third transistors are controlled to conduct so that said boost voltage is supplied to said bitline driver.
Claim 4
Dependent Claim
13 words
The apparatus recited in claim 2, wherein said third transistor is p-channel device.
Claim 5
Dependent Claim
41 words
The apparatus recited in claim 2, further comprising: a bistable latch coupled to said first data line and to said write enable line, wherein said data bit is latched, to said means for driving, when said write enable line is asserted.
Claim 6
Dependent Claim
63 words
The apparatus recited in claim 4, wherein: said bistable latch comprises first and second complementary write data outputs; said first and second complementary write data outputs are coupled to said means for driving; and said means for driving further comprises means driving each of said first and second complementary write data output to said bitline driver at a level of said boosted voltage.
Claim 7
Dependent Claim
54 words
The apparatus recited in claim 1, wherein said bitline driver comprises: first and second complementary drive input lines; first and second pairs of drive transistors each coupled to said first and second complementary drive input lines; and first and second complementary bitlines driven by one of said first and second pairs of drive transistors.
Claim 8
Dependent Claim
187 words
A memory array having a plurality of row lines, a plurality of bitline drivers that each generate complementary bitline signals on a pair of complementary bitlines, and memory cells coupled to said row lines and said bitlines at intersections thereof, a first write data line for receiving a data bit to be written to said bitline driver, and a second write data line providing a signal complementary to the data bit on said first write data line, the memory array comprising: a source of a boosted voltage; and driving circuit coupled to said first write data line, said second write data line, and said boosted voltage source for driving said data bit to said bitline driver at a level of said boosted voltages, said driving circuit including first and second complementary level shifters coupled respectively to said first and second write data lines, and each of said first and second level shifters including applying circuit coupled to a write enable line for applying said boosted voltage to said bitline driver when said write enable line and one of said first and second write data lines are asserted.
Claim 9
Dependent Claim
187 words
A memory array having a plurality of row lines, a plurality of bitline drivers that each generate complementary bitline signals on a pair of complementary bitlines, and memory cells coupled to said row lines and said bitlines at intersections thereof, a first write data line for receiving a data bit to be written to said bitline driver, and a second write data line providing a signal complementary to the data bit on said first write data line, the memory array comprising: a source of a boosted voltage; and driving circuit coupled to said first write data line, said second write data line, and said boosted voltage source for driving said data bit to said bitline driver at a level of said boosted voltages, said driving circuit including first and second complementary level shifters coupled respectively to said first and second write data lines, and each of said first and second level shifters including applying circuit coupled to a write enable line for applying said boosted voltage to said bitline driver when said write enable line and one of said first and second write data lines are asserted.
Claim 10
Dependent Claim
83 words
The memory array recited in claim 7, wherein said first level shifter comprises: a first transistor coupled to said first write data line; a second transistor coupled to said write enable line and to said first transistor; and a third transistor coupled to said boost voltage and to said second transistor; wherein, when said first write data line and said write enable line are asserted, said first, second and third transistors conduct so that said boost voltage is supplied to said bitline driver.
Claim 11
Dependent Claim
14 words
The memory array recited in claim 8, wherein said third transistor is p-channel device.
Claim 12
Dependent Claim
44 words
The memory array recited in claim 9, further comprising: a bistable latch coupled to said first data line and to a write enable line, wherein said data bit is latched and applied to said means for driving when said write enable line is asserted.
Claim 13
Dependent Claim
65 words
The memory array recited in claim 10, wherein: said bistable latch comprises first and second complementary write data outputs; said first and second complementary write data outputs are coupled to said means for driving; and said means for driving further comprises means for driving each of said first and second complementary write data outputs to said bitline driver at the level of said boosted voltage.
Claim 14
Dependent Claim
57 words
The memory array recited in claim 7, wherein said bitline driver comprises: first and second complementary drive input lines; first and second pairs of drive transistors coupled respectively to said first and second complementary drive input lines; and first and second complementary bitlines coupled to and driven respectively by said first and second pairs of drive transistors.
Claim 15
Independent Claim
85 words
A method of driving a bitline of a memory device, comprising the steps of: receiving a first data bit to be written to said bitline and a second data bit that is a complement of the first data bit; boosting one of the data bits to attain a boosted voltage of a magnitude greater than a supply voltage of the memory device; and driving the data bit that is boosted to a bitline driver coupled to the bitline at the level of the boosted voltage.
Claim 16
Independent Claim
85 words
A method of driving a bitline of a memory device, comprising the steps of: receiving a first data bit to be written to said bitline and a second data bit that is a complement of the first data bit; boosting one of the data bits to attain a boosted voltage of a magnitude greater than a supply voltage of the memory device; and driving the data bit that is boosted to a bitline driver coupled to the bitline at the level of the boosted voltage.
Claim 17
Dependent Claim
56 words
The method recited in claim 13, wherein the step of receiving the first data bit further comprises the step of: receiving a write enable signal indicating that the first data bit is to be written; and wherein the step of boosting one of the data bits is carried out in response to the write enable signal.
Claim 18
Dependent Claim
47 words
The method recited in claim 13, wherein the step of receiving a first data bit includes the steps of: receiving the first data bit at a bistable latch coupled to a write enable line; and latching the first data bit when the write enable line is asserted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |