Patent US5956493A successfully refreshed from Google Patents.
US5956493A
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Bus arbiter including programmable request latency counters for varying arbitration priority
Assignee: Advanced Micro Devices Inc
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Filing: 1996-03-08
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Granted: 1999-09-21
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Expires: 2016-03-08
Abstract
Abstract A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "request latency" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral requested ownership of the bus. An arbitration control unit is coupled to the request latency counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the latency signal corresponding to the device. Accordingly, as the time from when a peripheral device requests the bus increases, the level of arbitration priority given to that peripheral also increases. A set of programmable registers are provided to allow software programming of the initial count value associated with each request latency counter. The request latency counter for a particular device may further be held or inhibited from counting to provide a constant level of priority for that particular peripheral device.
Inventors
- 👤 Larry D. Hewitt
- 👤 Scott E. Swanstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
282 words
A bus arbiter for controlling and prioritizing ownership of a bus comprising: a request detection unit for detecting a plurality of bus request signals corresponding to designated bus masters; an arbitration control unit coupled to said request detection unit, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit and to control a granting of mastership of said bus to one of said designated bus masters; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first latency signal indicative of a first lapse of time following a request to obtain ownership of said bus by a first peripheral device which is one of said designated bus masters; a second counter unit coupled to said arbitration control unit wherein said second counter unit is configured to generate a second latency signal indicative of a second lapse of time following a request to obtain ownership of said bus by a second peripheral device which is another of said designated bus master; a programmable storage unit configured to store a first initial count value for said first counter unit and a second initial count value for said second counter unit; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said first peripheral device in response to said first latency signal indicating an increase in said first lapse of time; and wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said second peripheral device in response to said second latency signal indicating an increase in said second lapse of time.
Claim 2
Dependent Claim
282 words
A bus arbiter for controlling and prioritizing ownership of a bus comprising: a request detection unit for detecting a plurality of bus request signals corresponding to designated bus masters; an arbitration control unit coupled to said request detection unit, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit and to control a granting of mastership of said bus to one of said designated bus masters; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first latency signal indicative of a first lapse of time following a request to obtain ownership of said bus by a first peripheral device which is one of said designated bus masters; a second counter unit coupled to said arbitration control unit wherein said second counter unit is configured to generate a second latency signal indicative of a second lapse of time following a request to obtain ownership of said bus by a second peripheral device which is another of said designated bus master; a programmable storage unit configured to store a first initial count value for said first counter unit and a second initial count value for said second counter unit; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said first peripheral device in response to said first latency signal indicating an increase in said first lapse of time; and wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said second peripheral device in response to said second latency signal indicating an increase in said second lapse of time.
Claim 3
Dependent Claim
18 words
The bus arbiter as recited in claim 1 wherein said programmable storage unit includes a plurality of registers.
Claim 4
Dependent Claim
33 words
The bus arbiter as recited in claim 2 wherein each of said plurality of said registers is configured to store a parameter that controls whether an associated counter unit is inhibited from counting.
Claim 5
Dependent Claim
28 words
The bus arbiter as recited in claim 1 wherein said programmable storage unit is further configured to store a bit to inhibit said first counter unit from counting.
Claim 6
Dependent Claim
45 words
The bus arbiter as recited in claim 1 further comprising a decoder coupled to said programmable storage unit, wherein said decoder is configured to decode an address signal to thereby allow a setting of said first initial count value stored within said programmable storage unit.
Claim 7
Dependent Claim
42 words
The bus arbiter as recited in claim 1, wherein said arbitration control unit coupled to said request detection unit is configured to control a granting of mastership of said bus to one of said designated bus masters based upon an arbitration algorithm.
Claim 8
Dependent Claim
261 words
A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor through a CPU local bus; an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus; a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions; a non-real time master coupled to said expansion bus, wherein said non-real time master is configured to perform non-real time processing functions; and a bus arbiter for controlling and prioritizing ownership of said expansion bus including: a request detection unit for detecting a first request signal of said real time master and a second request signal of said non-real time master; an arbitration control unit coupled to said request detection unit, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit and to control a granting of mastership of said expansion bus to either said real time master or said non-real time master; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first latency signal indicative of a first lapse of time following a request to obtain ownership of said expansion bus by said real time master; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said real time master in response to said first latency signal indicating an increase in said first lapse of time.
Claim 9
Dependent Claim
261 words
A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor through a CPU local bus; an expansion bus coupled to said bus bridge, wherein said bus bridge is configured to accommodate data transfers between said CPU local bus and said expansion bus; a real time master coupled to said expansion bus, wherein said real time master is configured to perform real time processing functions; a non-real time master coupled to said expansion bus, wherein said non-real time master is configured to perform non-real time processing functions; and a bus arbiter for controlling and prioritizing ownership of said expansion bus including: a request detection unit for detecting a first request signal of said real time master and a second request signal of said non-real time master; an arbitration control unit coupled to said request detection unit, wherein said arbitration control unit is configured to process contending bus requests received by said request detection unit and to control a granting of mastership of said expansion bus to either said real time master or said non-real time master; and a first counter unit coupled to said arbitration control unit wherein said first counter unit is configured to generate a first latency signal indicative of a first lapse of time following a request to obtain ownership of said expansion bus by said real time master; wherein said arbitration control unit is further configured to increase a level of arbitration priority given to said real time master in response to said first latency signal indicating an increase in said first lapse of time.
Claim 10
Dependent Claim
49 words
The computer system as recited in claim 7, wherein said real time master is configured to assert a first request signal to request ownership of said expansion bus and wherein said non-real time master is configured to assert a second request signal to request ownership of said expansion bus.
Claim 11
Dependent Claim
16 words
The computer system as recited in claim 7 wherein said expansion bus is a PCI bus.
Claim 12
Dependent Claim
17 words
The computer system as recited in claim 7 wherein said real time master is an audio adapter.
Claim 13
Dependent Claim
55 words
The computer system as recited in claim 7 further comprising a second counter unit coupled to said arbitration control unit wherein said second counter unit is configured to generate a second latency signal indicative of a second lapse of time following a request to obtain ownership of said expansion bus by said non-real time master.
Claim 14
Dependent Claim
44 words
The computer system as recited in claim 11 wherein said arbitration control unit is configured to increase a level of arbitration priority given to said non-real time master in response to said second latency signal indicating an increase in said second lapse of time.
Claim 15
Dependent Claim
38 words
The computer system as recited in claim 12 further comprising a programmable storage unit configured to store a first initial count value for said first counter unit and a second initial count value for said second counter unit.
Claim 16
Dependent Claim
18 words
The computer system as recited in claim 13 wherein said programmable storage unit includes a plurality of registers.
Claim 17
Dependent Claim
33 words
The computer system as recited in claim 14 wherein each of said plurality of said registers is configured to store a parameter that controls whether an associated counter unit is inhibited from counting.
Claim 18
Dependent Claim
28 words
The computer system as recited in claim 13 wherein said programmable storage unit is further configured to store a bit to inhibit said first counter unit from counting.
Claim 19
Dependent Claim
45 words
The computer system as recited in claim 13 further comprising a decoder coupled to said programmable storage unit, wherein said decoder is configured to decode an address signal to thereby allow a setting of said first initial count value stored within said programmable storage unit.
Claim 20
Dependent Claim
41 words
The computer system as recited in claim 7, wherein said arbitration control unit is configured to control a granting of mastership of said expansion bus to either said real time master or said non-real time master based upon an arbitration algorithm.
References Cited (Backward Citations)
US4339808A
Cited
US4682282A
Cited
US4974148A
Cited
JPH0248765A
Cited
US4972313A
Cited
US5146596A
Cited
WO1993016434A1
Cited
US5392033A
Cited
EP0629955A1
Cited
US5396602A
Cited
US5471590A
Cited
US5535341A
Cited
US5533205A
Cited
US5463624A
Cited
US5546546A
Cited
US5574867A
Cited
US5524235A
Cited
US5572686A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |