Patent US6021050A successfully refreshed from Google Patents.
US6021050A
Expired / Lapsed
US
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Printed circuit boards with integrated passive components and method for making same
Assignee: Bourns Inc
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Filing: 1998-12-02
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Granted: 2000-02-01
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Expires: 2018-12-02
Abstract
Abstract A multi-layered printed circuit board having a plurality of burried passive elements and a method for producing the circuit board wherein the passive elements can include resistors, capacitors and inductors. The method includes the steps of manufacturing individual layers of the multi-layer printed circuit board with electrical circuits thereon and subsequently screening polymer inks having resistive, dielectric or magnetic values to form the resistors, capacitors and inductors. Each layer of the circuit board is cured to dry the polymer ink and thereafter the individual layers are bonded together to form the multi-layer board.
Inventors
- 👤 Michael F. Ehman
- 👤 Larry L. Eslinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:01
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/16; H05K1/165; H05K1/162; H05K1/02; H05K1/09; H05K1/092; H05K1/095; H05K1/167; H05K2201/00; H05K2201/01; H05K2201/0183; H05K2201/0187; H05K2201/02; H05K2201/0203; H05K2201/0206; H05K2201/0209; H05K2201/08; H05K2201/083; H05K2201/086; H05K2203/00; H05K2203/05; H05K2203/0502; H05K2203/0545; H05K3/00; H05K3/46; H05K3/4611; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917; Y10T428/24926
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
115 words
A multi-layer printed circuit board having a plurality of buried passive elements comprising: a plurality of circuit board layers bonded together; at least one electrical circuit on each layer; a polymer ink resistor screened on at least one of the layers in electrical contact with the electrical circuit; a capacitor having an upper capacitor plate and a lower capacitor plate formed in the electrical circuits of adjacent circuit board layers and a polymeric ink dielectric screened between the upper and lower capacitor plates; and an inductor element formed in the electrical circuit of a circuit board layer and a polymeric ink layer screened on an adjacent circuit board layer in line with the inductor element.
Claim 2
Dependent Claim
115 words
A multi-layer printed circuit board having a plurality of buried passive elements comprising: a plurality of circuit board layers bonded together; at least one electrical circuit on each layer; a polymer ink resistor screened on at least one of the layers in electrical contact with the electrical circuit; a capacitor having an upper capacitor plate and a lower capacitor plate formed in the electrical circuits of adjacent circuit board layers and a polymeric ink dielectric screened between the upper and lower capacitor plates; and an inductor element formed in the electrical circuit of a circuit board layer and a polymeric ink layer screened on an adjacent circuit board layer in line with the inductor element.
Claim 3
Dependent Claim
18 words
The printed circuit board of claim 1 further having a bonding agent between adjacent printed circuit board layers.
Claim 4
Dependent Claim
25 words
The printed circuit board of claim 1 wherein the circuit board layers have an electrical circuit on an upper surface and on a lower surface.
Claim 5
Dependent Claim
17 words
The printed circuit board of claim 1 wherein the capacitor plates are integral with the electrical circuit.
Claim 6
Dependent Claim
14 words
The printed circuit board of claim 1 wherein the polymeric ink layer is magnetic.
Claim 7
Dependent Claim
14 words
The printed circuit board of claim 1 wherein the polymeric ink layer is ferrite.
Claim 8
Dependent Claim
110 words
A multi-layer printed circuit board comprising: a plurality of circuit board layers bonded together; an electrical circuit on an upper surface and a lower surface of each printed circuit board layer; a first buried passive element screened in electrical contact with the electrical circuits between adjacent circuit board layers; and a second and different buried passive element screened in electrical contact with the electrical circuits between adjacent circuit board layers, wherein the second passive element is an inductor having an inductor element formed in the electrical circuit of a circuit board layer and a polymeric ink layer screened on an adjacent circuit board layer in line with the inductor element.
Claim 9
Dependent Claim
110 words
A multi-layer printed circuit board comprising: a plurality of circuit board layers bonded together; an electrical circuit on an upper surface and a lower surface of each printed circuit board layer; a first buried passive element screened in electrical contact with the electrical circuits between adjacent circuit board layers; and a second and different buried passive element screened in electrical contact with the electrical circuits between adjacent circuit board layers, wherein the second passive element is an inductor having an inductor element formed in the electrical circuit of a circuit board layer and a polymeric ink layer screened on an adjacent circuit board layer in line with the inductor element.
Claim 10
Dependent Claim
15 words
The printed circuit board of claim 7 wherein the first passive element is a resistor.
Claim 11
Dependent Claim
48 words
The printed circuit board of claim 7 wherein the first passive element is a capacitor having an upper capacitor plate and a lower capacitor plate formed in the electrical circuits of adjacent circuit board layers and a polymeric ink dielectric screened between the upper and lower capacitor plates.
Claim 12
Dependent Claim
21 words
The printed circuit board of claim 9 further comprising a third buried passive element positioned between adjacent printed circuit board layers.
Claim 13
Dependent Claim
15 words
The printed circuit board of claim 10 wherein the third passive element comprises a resistor.
Claim 14
Independent Claim
137 words
A method for producing a printed circuit board having a plurality of circuit board layers comprising: generating electrical circuits on each individual circuit board layer, the electrical circuits having portions to accommodate passive components; depositing a first polymer ink on the electrical circuits to form at least one first passive component; curing the first polymer ink; depositing a second and different polymer ink on the electrical circuits to form at least one second passive component, wherein the second passive component is an inductor having an inductor element formed in the electrical circuit of one of the circuit board layers and wherein the polymer ink is screened on an adjacent circuit board layer in line with the inductor element; curing the second polymer ink; and bonding the circuit board layers together to form a multi-layer printed circuit board.
Claim 15
Independent Claim
137 words
A method for producing a printed circuit board having a plurality of circuit board layers comprising: generating electrical circuits on each individual circuit board layer, the electrical circuits having portions to accommodate passive components; depositing a first polymer ink on the electrical circuits to form at least one first passive component; curing the first polymer ink; depositing a second and different polymer ink on the electrical circuits to form at least one second passive component, wherein the second passive component is an inductor having an inductor element formed in the electrical circuit of one of the circuit board layers and wherein the polymer ink is screened on an adjacent circuit board layer in line with the inductor element; curing the second polymer ink; and bonding the circuit board layers together to form a multi-layer printed circuit board.
Claim 16
Dependent Claim
23 words
The method of claim 12 wherein the first polymer ink is a polymer dielectric ink and the first passive component is a capacitor.
Claim 17
Dependent Claim
23 words
The method of claim 12 wherein the first polymer ink is a polymer resistor ink and the first passive component is a resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |