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US6060360A
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Method of manufacture of P-channel EEprom and flash EEprom devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-04-14
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Granted: 2000-05-09
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Expires: 2017-04-14
Abstract
Abstract A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
Inventors
- 👤 Yai-Fen Lin
- 👤 Shiou-Hann Liaw
- 👤 Di-Son Kuo
- 👤 Juang-Ke Yeh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
218 words
A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate comprising an N-well doped with a first, N-type of dopant, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming a floating gate electrode layer comprising a polysilicon layer over said tunnel oxide layer and then doping said floating gate electrode layer with said first, N-type of dopant, then forming an interelectrode dielectric layer over said floating gate electrode, then forming a control gate electrode layer including a layer composed of polysilicon over said interelectrode dielectric layer and then counterdoping said control gate electrode with an opposite, P-type of dopant, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer and, said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and then performing an ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite, P-type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack.
Claim 2
Independent Claim
218 words
A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate comprising an N-well doped with a first, N-type of dopant, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming a floating gate electrode layer comprising a polysilicon layer over said tunnel oxide layer and then doping said floating gate electrode layer with said first, N-type of dopant, then forming an interelectrode dielectric layer over said floating gate electrode, then forming a control gate electrode layer including a layer composed of polysilicon over said interelectrode dielectric layer and then counterdoping said control gate electrode with an opposite, P-type of dopant, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer and, said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and then performing an ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite, P-type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack.
Claim 3
Dependent Claim
43 words
The method of claim 1 wherein: said floating gate electrode layer is a laminated structure comprising: an undoped lower polysilicon layer, said doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer formed on said doped polysilicon layer.
Claim 4
Dependent Claim
50 words
The method of claim 1 wherein: said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein: said floating gate electrode layer has a thickness from about 1,000 Å to about 1,200 Å.
Claim 6
Dependent Claim
71 words
The method of claim 1 wherein said floating gate electrode layer is a laminated structure comprising: a lower, undoped polysilicon layer having a thickness from about 1,000 Å to about 1200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1200 Å, and an upper, undoped polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å.
Claim 7
Dependent Claim
54 words
The method of claim 1 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, and said tunnel oxide layer has a thickness from about 90 Å to about 100 Å.
Claim 8
Dependent Claim
98 words
The method of claim 1 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 9
Dependent Claim
131 words
The method of claim 1 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an undoped upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 10
Dependent Claim
176 words
The method of claim 1 wherein: said floating gate electrode layer is a laminated structure comprising a lower polysilicon undoped layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an undoped upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said sour ce/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 , and said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm 2 to about 1.4 E 13 ions/cm 2 .
Claim 11
Independent Claim
262 words
A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming a floating gate electrode layer including a first doped polysilicon layer with said first type of dopant over said tunnel oxide layer, patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width, then forming an interelectrode dielectric layer over said floating gate electrode and the exposed portion of said tunnel oxide, then forming a control gate electrode layer including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layer, thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode into a gate electrode stack above said channel, and then performing a self-aligned ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.
Claim 12
Independent Claim
262 words
A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming a floating gate electrode layer including a first doped polysilicon layer with said first type of dopant over said tunnel oxide layer, patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width, then forming an interelectrode dielectric layer over said floating gate electrode and the exposed portion of said tunnel oxide, then forming a control gate electrode layer including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layer, thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode into a gate electrode stack above said channel, and then performing a self-aligned ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.
Claim 13
Dependent Claim
44 words
The method of claim 10 wherein said floating gate electrode layer is a laminated structure comprising: an undoped lower polysilicon layer, said first doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer formed on said counterdoped polysilicon layer.
Claim 14
Dependent Claim
50 words
The method of claim 10 wherein: said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 15
Dependent Claim
22 words
The method of claim 10 wherein: said floating gate electrode layer has a thickness from about 1,000 Å to about 1,200 Å.
Claim 16
Dependent Claim
70 words
The method of claim 10 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, a doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an undoped upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å.
Claim 17
Dependent Claim
53 words
The method of claim 10 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer, a doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, and said tunnel oxide layer has a thickness from about 90 Å to about 100 Å.
Claim 18
Dependent Claim
97 words
The method of claim 10 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer, a doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 19
Dependent Claim
131 words
The method of claim 10 wherein: said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and an undoped upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 20
Dependent Claim
49 words
The method of claim 10 wherein: said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm 2 to about 1.4 E 13 ions/cm 2 .
Claim 21
Independent Claim
244 words
A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant by the steps comprising: forming a tunnel oxide layer over said substrate, then forming floating gate electrode layers over said tunnel oxide layer, by the steps comprising: a) forming a lower, undoped polysilicon layer, b) then forming a doped polysilicon layer formed on said lower polysilicon layer doped with said first type of dopant, and c) then forming an upper, undoped polysilicon layer formed on said doped polysilicon layer, then forming an interelectrode dielectric layer over said floating gate electrode layers, then forming a control gate electrode layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and then performing a self-aligned ion implanting doping step in which a source region and a drain region are formed by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack.
Claim 22
Independent Claim
244 words
A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant by the steps comprising: forming a tunnel oxide layer over said substrate, then forming floating gate electrode layers over said tunnel oxide layer, by the steps comprising: a) forming a lower, undoped polysilicon layer, b) then forming a doped polysilicon layer formed on said lower polysilicon layer doped with said first type of dopant, and c) then forming an upper, undoped polysilicon layer formed on said doped polysilicon layer, then forming an interelectrode dielectric layer over said floating gate electrode layers, then forming a control gate electrode layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and then performing a self-aligned ion implanting doping step in which a source region and a drain region are formed by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, whereby said source region and said drain region are self-aligned with said gate electrode stack.
Claim 23
Dependent Claim
50 words
The method of claim 19 wherein: said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 24
Dependent Claim
23 words
The method of claim 19 wherein said doped floating gate electrode layer has a thickness from about 1,000 Å to about 1,200 Å.
Claim 25
Dependent Claim
68 words
The method of claim 19 wherein said floating gate electrode layers are a laminated structure comprising: said lower, undoped polysilicon layer which has a thickness from about 1,000 Å to about 1200 Å, said N+ doped polysilicon layer which has a thickness from about 1,000 Å to about 1200 Å, and said upper, undoped polysilicon layer which has a thickness from about 2,000 Å to about 3,000 Å.
Claim 26
Dependent Claim
54 words
The method of claim 19 wherein: said floating gate electrode layers are a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, and said tunnel oxide layer has a thickness from about 90 Å to about 100 Å.
Claim 27
Dependent Claim
98 words
The method of claim 19 wherein: said floating gate electrode layers are a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 28
Dependent Claim
134 words
The method of claim 19 wherein: said floating gate electrode layers are a laminated structure comprising: a) an undoped lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, b) an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å to about 1,200 Å, and e) an undoped upper polysilicon layer having a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 29
Dependent Claim
180 words
The method of claim 19 wherein: said floating gate electrode layers are a laminated structure comprising: a) said lower polysilicon undoped layer which has a thickness from about 1,000 Å to about 1,200 Å, b) said doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å to about 1,200 Å, and c) said undoped upper polysilicon layer which has a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 , and said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm 2 to about 1.4 E 13 ions/cm 2 .
Claim 30
Independent Claim
290 words
A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming floating gate electrode layers over said tunnel oxide layer, comprising forming a lower, undoped polysilicon layer, forming a doped polysilicon layer doped with said first type of dopant on said lower polysilicon layer, and forming an upper, undoped polysilicon layer formed on said doped polysilicon layer, patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width, then forming an interelectrode dielectric layer over said floating gate electrode layers and the exposed portion of said tunnel oxide, then forming a control gate electrode including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack above said channel, and then performing a self-aligned ion implanting doping step in which a source region and a drain region are forming by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, and whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.
Claim 31
Independent Claim
290 words
A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising: forming a tunnel oxide layer over said substrate, then forming floating gate electrode layers over said tunnel oxide layer, comprising forming a lower, undoped polysilicon layer, forming a doped polysilicon layer doped with said first type of dopant on said lower polysilicon layer, and forming an upper, undoped polysilicon layer formed on said doped polysilicon layer, patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width, then forming an interelectrode dielectric layer over said floating gate electrode layers and the exposed portion of said tunnel oxide, then forming a control gate electrode including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer, then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack above said channel, and then performing a self-aligned ion implanting doping step in which a source region and a drain region are forming by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, and whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.
Claim 32
Dependent Claim
50 words
The method of claim 27 wherein: said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 33
Dependent Claim
22 words
The method of claim 27 wherein: said floating gate electrode layer has a thickness from about 1,000 Å to about 1,200 Å.
Claim 34
Dependent Claim
73 words
The method of claim 27 wherein: said floating gate electrode layers are a laminated structure comprising: an undoped lower polysilicon layer which has a thickness from about 1,000 Å to about 1,200 Å, a doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å to about 1,200 Å, and an undoped upper polysilicon layer which has a thickness from about 2,000 Å to about 3,000 Å.
Claim 35
Dependent Claim
21 words
The method of claim 27 wherein: said tunnel oxide layer has a thickness from about 90 Å to about 100 Å.
Claim 36
Dependent Claim
66 words
The method of claim 27 wherein: said tunnel oxide layer has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 37
Dependent Claim
134 words
The method of claim 27 wherein: said floating gate electrode layers are a laminated structure comprising: said undoped lower polysilicon layer which has a thickness from about 1,000 Å to about 1,200 Å, said doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å to about 1,200 Å, and said undoped upper polysilicon layer which has a thickness from about 2,000 Å to about 3,000 Å, said tunnel oxide layer which has a thickness from about 90 Å to about 100 Å, and said source/drain dopant comprises P type dopant ions of boron fluoride, BF 2 , ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm 2 to about 5 E 15 ions/cm 2 .
Claim 38
Dependent Claim
49 words
The method of claim 27 wherein: said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm 2 to about 1.4 E 13 ions/cm 2 .
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