US6124199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for simultaneously forming a storage-capacitor electrode and interconnect
Assignee: GlobalFoundries Inc
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Filing: 1999-04-28
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Granted: 2000-09-26
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Expires: 2019-04-28
Abstract
Abstract A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
Inventors
- 👤 Jeffrey P. Gambino
- 👤 Gary B. Bronner
- 👤 David E. Kotecki
- 👤 Carl J. Radens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:24
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10B12/30; H10B12/48; H10B12/482; H10W; H10W20/00; H10W20/40; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
118 words
A method for making a memory cell, comprising: forming a first layer including a transfer gate; forming a second layer which includes a first signal line forming a third layer which includes a storage capacitor connected to the transfer gate in said first layer, said third layer further being formed by: (a) depositing a lower capacitor electrode adjacent said storage capacitor, (b) laying a dielectric material over said lower capacitor electrode, and (c) depositing an upper capacitor electrode over said dielectric material and said lower capacitor electrode; depositing a second signal line on said third layer; and connecting said first signal line and said second line through one of said lower capacitor electrode and said upper capacitor electrode.
Claim 2
Independent Claim
118 words
A method for making a memory cell, comprising: forming a first layer including a transfer gate; forming a second layer which includes a first signal line forming a third layer which includes a storage capacitor connected to the transfer gate in said first layer, said third layer further being formed by: (a) depositing a lower capacitor electrode adjacent said storage capacitor, (b) laying a dielectric material over said lower capacitor electrode, and (c) depositing an upper capacitor electrode over said dielectric material and said lower capacitor electrode; depositing a second signal line on said third layer; and connecting said first signal line and said second line through one of said lower capacitor electrode and said upper capacitor electrode.
Claim 3
Dependent Claim
32 words
The method of claim 1, wherein said step of forming said third layer includes: forming said lower capacitor electrode and a first electrode of said storage capacitor simultaneously in a same plane.
Claim 4
Dependent Claim
35 words
The method of claim 1, wherein a dielectric of said storage capacitor is made from a same material as said dielectric layer, said dielectric layer and the dielectric of said storage capacitor being laid simultaneously.
Claim 5
Dependent Claim
32 words
The method of claim 3, wherein said step of forming said third layer includes: forming said upper capacitor electrode and a second electrode of said storage capacitor simultaneously in a same plane.
Claim 6
Dependent Claim
42 words
The method of claim 4, wherein said lower capacitor electrode and the first electrode of said storage capacitor are made from a same material selected from a group consisting of Pt, Ir, IrO 2 , RuO 2 , and SrRuO 3 .
Claim 7
Dependent Claim
22 words
The method of claim 3, further comprising: wherein said step of depositing said upper capacitor electrode is performed by a damascene process.
Claim 8
Dependent Claim
55 words
The method of claim 6, further comprising: etching a hole through said upper capacitor electrode and said dielectric layer, said etching step stopping at a top surface of said lower capacitor electrode; and filling said hole with a conductive material to form a stud for connecting said lower capacitor electrode with said second signal line.
Claim 9
Dependent Claim
37 words
The method of claim 7, further comprising: depositing a third signal line and a fourth signal line on said third layer; and connecting said third signal line and said fourth signal line through said upper capacitor electrode.
Claim 10
Dependent Claim
14 words
The method of claim 1, wherein said memory cell is a DRAM memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-26 | 2004-03-27 | 2004-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-26 | 2008-03-27 | 2008-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-26 | 2012-03-27 | 2012-09-26 | $7700.00 | Window Closed / Lapsed |