US6407953B1 — Memory array organization and related test method…

Claim 1

Independent Claim 176 words

In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of: providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, to ascertain at least one characteristic of the test memory cells; and using the at least one ascertained characteristic of the test memory cells to predict whether related memory cells in the array will program correctly.

Claim 2

Dependent Claim 176 words

In an integrated circuit including a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of: providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, to ascertain at least one characteristic of the test memory cells; and using the at least one ascertained characteristic of the test memory cells to predict whether related memory cells in the array will program correctly.

Claim 3

Dependent Claim 29 words

The method as recited in claim 1 wherein: each of the first and second plurality of test memory cells is characteristically identical to the memory cells of the array.

Claim 4

Dependent Claim 31 words

The method as recited in claim 1 wherein: each of the first and second plurality of test memory cells is characteristically similar but not identical to memory cells of the array.

Claim 5

Dependent Claim 20 words

The method as recited in claim 1 wherein: every respective word line has a respective test memory cell connected thereto.

Claim 6

Dependent Claim 20 words

The method as recited in claim 1 wherein: every respective bit line has a respective test memory cell connected thereto.

Claim 7

Dependent Claim 16 words

The method as recited in claim 1 wherein: the memory array comprises a three-dimensional memory array.

Claim 8

Dependent Claim 45 words

The method as recited in claim 1 wherein: the biasing step comprises impressing a particular voltage across a given test memory cell sufficient to program the test memory cell; and the at least one characteristic comprises whether the given test memory cell is successfully programmed.

Claim 9

Dependent Claim 50 words

The method as recited in claim 1 wherein: the biasing step comprises impressing a particular voltage across a given test memory cell below that sufficient to program the test memory cell; and the at least one characteristic comprises a measured leakage current through the given test memory cell under bias.

Claim 10

Dependent Claim 28 words

The method as recited in claim 1 wherein: the predetermined ones of the first and second plurality of test memory cells comprise all of the test memory cells.

Claim 11

Dependent Claim 31 words

The method as recited in claim 1 wherein: the predetermined ones of the first and second plurality of test memory cells comprise some but not all of the test memory cells.

Claim 12

Dependent Claim 77 words

The method as recited in claim 1 wherein the biasing step comprises: sequentially driving each respective word line to a first predetermined voltage while driving its associated test bit line to a second predetermined voltage to bias each respective test memory cell connected therebetween; and sequentially driving each respective bit line to the second predetermined voltage while driving its associated test word line to the first predetermined voltage to bias each respective test memory cell connected therebetween.

Claim 13

Dependent Claim 83 words

The method as recited in claim 1 wherein: each respective one of the first plurality of test memory cells is connected to its respective word line on an opposite side of the memory array relative to a respective programming driver for the respective word line; and each respective one of the second plurality of test memory cells is connected to its respective bit line on an opposite side of the memory array relative to a respective programming driver for the respective bit line.

Claim 14

Dependent Claim 150 words

In an integrated circuit including a programmable memory array of programmable memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of: providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; programming each test memory cell; predicting which memory cells in the array will correctly program based upon which test memory cells are successfully programmed during the programming step, without actually programming any memory cells.

Claim 15

Dependent Claim 150 words

In an integrated circuit including a programmable memory array of programmable memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines, a test method comprising the steps of: providing at least one test word line and at least one test bit line for the array; providing a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; providing a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; programming each test memory cell; predicting which memory cells in the array will correctly program based upon which test memory cells are successfully programmed during the programming step, without actually programming any memory cells.

Claim 16

Dependent Claim 29 words

The method as recited in claim 13 further comprising: reading unprogrammed memory cells before and after programming certain test memory cells to confirm operation of memory array read circuitry.

Claim 17

Dependent Claim 16 words

The method as recited in claim 13 wherein: the memory array is a one-time programmable array.

Claim 18

Dependent Claim 22 words

The method as recited in claim 13 wherein: the memory array is three-dimensional array having at least two planes of memory cells.

Claim 19

Dependent Claim 16 words

The method as recited in claim 16 wherein: the memory array is a one-time programmable array.

Claim 20

Dependent Claim 37 words

The method as recited in claim 13 wherein: each test memory cell coupled to a test bit line is coupled to its respective word line at an end opposite a programming driver for the respective word line.

Claim 21

Dependent Claim 37 words

The method as recited in claim 13 wherein: each test memory cell coupled to a test word line is coupled to its respective bit line at an end opposite a programming driver for the respective bit line.

Claim 22

Dependent Claim 71 words

The method as recited in claim 13 further comprising: biasing each respective word line and bit line, in groups of at least one such line at a time, to a voltage different from that of its adjacent conductive lines; determining whether leakage current exceeding a predetermined value is supported by a group of biased lines; and qualifying at least one attribute of the memory array based upon the leakage current determinations.

Claim 23

Dependent Claim 60 words

The method as recited in claim 13 further comprising: impressing a particular voltage across respective memory cells below that sufficient to program the memory cells; and predicting whether a respective memory cell in the array will correctly program based at least in part upon the magnitude of any leakage current flowing through the respective memory cell during the impressing step.

Claim 24

Dependent Claim 23 words

The method as recited in claim 21 wherein: the particular voltage is approximately 60-80% of an expected programming voltage for the memory cells.

Claim 25

Dependent Claim 157 words

An integrated circuit comprising: a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines; at least one test word line and at least one test bit line for the array; a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; terminal circuitry for biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, and for ascertaining at least one characteristic of the test memory cells useful for predicting whether related memory cells in the array will program correctly.

Claim 26

Dependent Claim 157 words

An integrated circuit comprising: a write-once memory array of memory cells, each respectively coupled between a respective one of a plurality of word lines and a respective one of a plurality of bit lines; at least one test word line and at least one test bit line for the array; a first plurality of test memory cells, each respectively connected between a respective word line and an associated one of the at least one test bit line; a second plurality of test memory cells, each respectively connected between a respective bit line and an associated one of the at least one test word line; terminal circuitry for biasing predetermined ones of the first and second plurality of test memory cells, in groups of at least one test memory cell at a time, and for ascertaining at least one characteristic of the test memory cells useful for predicting whether related memory cells in the array will program correctly.

Claim 27

Dependent Claim 30 words

The integrated circuit as recited in claim 23 wherein: each of the first and second plurality of test memory cells is characteristically identical to the memory cells of the array.

Claim 28

Dependent Claim 32 words

The integrated circuit as recited in claim 23 wherein: each of the first and second plurality of test memory cells is characteristically similar but not identical to memory cells of the array.

Claim 29

Dependent Claim 21 words

The integrated circuit as recited in claim 23 wherein: every respective word line has a respective test memory cell connected thereto.

Claim 30

Dependent Claim 21 words

The integrated circuit as recited in claim 23 wherein: every respective bit line has a respective test memory cell connected thereto.

Claim 31

Dependent Claim 17 words

The integrated circuit as recited in claim 23 wherein: the memory array comprises a three-dimensional memory array.

Claim 32

Dependent Claim 48 words

The integrated circuit as recited in claim 23 wherein: the terminal circuitry is arranged to impress a particular voltage across a given test memory cell sufficient to program the test memory cell; and the at least one characteristic comprises whether the given test memory cell is successfully programmed.

Claim 33

Dependent Claim 53 words

The integrated circuit as recited in claim 23 wherein: the terminal circuitry is arranged to impress a particular voltage across a given test memory cell below that sufficient to program the test memory cell; and the at least one characteristic comprises a measured leakage current through the given test memory cell under bias.

Claim 34

Dependent Claim 29 words

The integrated circuit as recited in claim 23 wherein: the predetermined ones of the first and second plurality of test memory cells comprise all of the test memory cells.

Claim 35

Dependent Claim 32 words

The integrated circuit as recited in claim 23 wherein: the predetermined ones of the first and second plurality of test memory cells comprise some but not all of the test memory cells.

Claim 36

Dependent Claim 86 words

The integrated circuit as recited in claim 23 wherein: the terminal circuitry is arranged to sequentially drive each respective word line to a first predetermined voltage and drive its associated test bit line to a second predetermined voltage, to bias each respective test memory cell connected therebetween; and the terminal circuitry is arranged to sequentially drive each respective bit line to the second predetermined voltage and drive its associated test word line to the first predetermined voltage, to bias each respective test memory cell connected therebetween.

Claim 37

Dependent Claim 84 words

The integrated circuit as recited in claim 23 wherein: each respective one of the first plurality of test memory cells is connected to its respective word line on an opposite side of the memory array relative to a respective programming driver for the respective word line; and each respective one of the second plurality of test memory cells is connected to its respective bit line on an opposite side of the memory array relative to a respective programming driver for the respective bit line.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2005-06-17	2005-12-17	2006-06-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2009-06-17	2009-12-17	2010-06-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2013-06-17	2013-12-17	2014-06-18	$7700.00	Window Closed / Lapsed

Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

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