Patent US6489664B2 successfully refreshed from Google Patents.
US6489664B2
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Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors
Assignee: STMicroelectronics SRL
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Filing: 2001-05-24
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Granted: 2002-12-03
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Expires: 2021-05-24
Abstract
Abstract A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.
Inventors
- 👤 Danilo Re
- 👤 Massimo Monselice
- 👤 Paola Maria Granatieri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:25
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/80; H10D84/811; H10D84/817
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
172 words
An integrated MOS device, comprising: a single-crystal silicon body; gate regions including a region of a polysilicon layer and a metal silicide layer arranged on the polysilicon region and insulated from said single-crystal silicon body by first isolating regions, said gate regions having a first resistivity and the polysilicon region accommodating first and second doping impurities and having a second resistivity greater than the first resistivity; and a first resistive element formed of regions of the polysilicon layer and a conductive layer and a second resistive element formed of the polysilicon layer and arranged on and insulated from said single-crystal silicon body by second isolating regions, said first resistive element accommodating the first and second doping impurities and having the second resistivity, and said second resistive element accommodating only the first doping impurity and having a third resistivity higher than said second resistivity, wherein said first resistive element and said second resistive element extend on top of field isolating regions and the first and second impurities are of an opposite conductivity type.
Claim 2
Dependent Claim
172 words
An integrated MOS device, comprising: a single-crystal silicon body; gate regions including a region of a polysilicon layer and a metal silicide layer arranged on the polysilicon region and insulated from said single-crystal silicon body by first isolating regions, said gate regions having a first resistivity and the polysilicon region accommodating first and second doping impurities and having a second resistivity greater than the first resistivity; and a first resistive element formed of regions of the polysilicon layer and a conductive layer and a second resistive element formed of the polysilicon layer and arranged on and insulated from said single-crystal silicon body by second isolating regions, said first resistive element accommodating the first and second doping impurities and having the second resistivity, and said second resistive element accommodating only the first doping impurity and having a third resistivity higher than said second resistivity, wherein said first resistive element and said second resistive element extend on top of field isolating regions and the first and second impurities are of an opposite conductivity type.
Claim 3
Dependent Claim
16 words
A device according to claim 1 wherein said second resistivity is between 20 and 400 Ohms/square.
Claim 4
Dependent Claim
16 words
A device according to claim 1 wherein said third resistivity is between 500 and 3000 Ohms/square.
Claim 5
Dependent Claim
169 words
An integrated circuit, comprising: a semiconductor substrate; first and second insulation regions on the substrate; a first resistive region including a first portion of a polycrystalline semiconductor layer, the first portion of the polycrystalline semiconductor layer accommodating first and second doping impurities and separated from the substrate by the first insulation region, the first resistive region having a first resistivity; a second resistive region including a second portion of the polycrystalline semiconductor layer, the second portion of the polycrystalline semiconductor layer accommodating only the first doping impurity and separated from the substrate by the first insulation region, the second resistive region having a second resistivity less than the first resistivity; and a gate region including a conductive layer and a third portion of the polycrystalline semiconductor layer, the third portion of the polycrystalline semiconductor layer accommodating the first and second doping impurities to have the second resistivity and separated from the substrate by the second insulation region, the gate region having a third resistivity less than the second resistivity
Claim 6
Dependent Claim
169 words
An integrated circuit, comprising: a semiconductor substrate; first and second insulation regions on the substrate; a first resistive region including a first portion of a polycrystalline semiconductor layer, the first portion of the polycrystalline semiconductor layer accommodating first and second doping impurities and separated from the substrate by the first insulation region, the first resistive region having a first resistivity; a second resistive region including a second portion of the polycrystalline semiconductor layer, the second portion of the polycrystalline semiconductor layer accommodating only the first doping impurity and separated from the substrate by the first insulation region, the second resistive region having a second resistivity less than the first resistivity; and a gate region including a conductive layer and a third portion of the polycrystalline semiconductor layer, the third portion of the polycrystalline semiconductor layer accommodating the first and second doping impurities to have the second resistivity and separated from the substrate by the second insulation region, the gate region having a third resistivity less than the second resistivity
Claim 7
Dependent Claim
20 words
The integrated circuit of claim 4 wherein the first and second insulation regions include field-oxide and gate oxide layers, respectively.
Claim 8
Dependent Claim
15 words
The integrated circuit of claim 4 wherein the polycrystalline semiconductor layer includes a polysilicon layer.
Claim 9
Dependent Claim
25 words
The integrated circuit of claim 4 wherein the polycrystalline semiconductor layer includes a polysilicon layer, and wherein the conducting layer includes a metal silicide layer.
Claim 10
Dependent Claim
17 words
The integrated circuit of claim 4 wherein the first and second doping impurities are of opposite type.
Claim 11
Dependent Claim
25 words
The integrated circuit of claim 4 , wherein the first doping impurity is of N type and the second doping impurity is of P type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-12-02 | 2006-06-03 | 2006-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-02 | 2010-06-03 | 2010-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-02 | 2014-06-03 | 2014-12-03 | $7700.00 | Window Closed / Lapsed |