US6531350B2
Expired / Lapsed
US
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Twin MONOS cell fabrication method and array organization
Assignee: Halo LSI Design and Device Technology Inc
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Filing: 2001-11-21
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Granted: 2003-03-11
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Expires: 2021-11-21
Abstract
Abstract Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.
Inventors
- 👤 Kimihiro Satoh
- 👤 Seiki Ogura
- 👤 Tomoya Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:13
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10D; H10D30/00; H10D30/60; H10D30/68; H10B43/40; H10D30/01; H10D30/021; H10D30/0413; H10D30/69; H10D30/691; Y; Y10; Y10S; Y10S257/00; Y10S257/906; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 57
Claim 1
Independent Claim
248 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; simultaneously defining a logic gate in said logic-area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure wherein said polysilicon spacers form control gates in said memory area; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates and said source/drain region in said logic area; and depositing an oxide layer overlying said salicided gates and source/drain regions to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 2
Independent Claim
248 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; simultaneously defining a logic gate in said logic-area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure wherein said polysilicon spacers form control gates in said memory area; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates and said source/drain region in said logic area; and depositing an oxide layer overlying said salicided gates and source/drain regions to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 3
Dependent Claim
132 words
The method according to claim 1 wherein said step of simultaneously defining a logic gate in said logic area and a memory gate in said memory area comprises: forming said gate oxide layer on said substrate; depositing said first conducting layer overlying said gate oxide layer; depositing said cap nitride layer overlying said first conducting layer in said memory area; patterning said first and second cap oxide layers and said cap nitride layer to form a hard mask wherein said first and second cap oxide layers form said hard mask; and etching away said cap nitride layer, said first conducting layer, and said gate oxide layer where they are not covered by said hard mask to form said memory gate in said memory area and said logic gate in said logic area.
Claim 4
Dependent Claim
21 words
The method according to claim 1 wherein said gate oxide layer has a thickness of between about 2 and 10 nanometers.
Claim 5
Dependent Claim
23 words
The method according to claim 1 wherein said first conducting layer comprises polysilicon having a thickness of between about 150 and 250 nm.
Claim 6
Dependent Claim
21 words
The method according to claim 2 wherein said first and second cap oxide layers have a thickness of about 30 nm.
Claim 7
Dependent Claim
21 words
The method according to claim 1 wherein said cap nitride layer has a thickness of between about 100 and 200 nm.
Claim 8
Dependent Claim
60 words
The method according to claim 2 wherein said step of etching away said cap nitride layer, said first conducting layer, and said gate oxide layer is a reactive ion etch wherein the etch rate of nitride is close to the etch rate of polysilicon and wherein the etch rate of oxide is much slower than the etch rate of polysilicon.
Claim 9
Dependent Claim
146 words
The method according to claim 1 wherein said step of simultaneously defining a logic gate in said logic area and a memory gate in said memory area comprises: forming said gate oxide layer on said substrate; depositing said first conducting layer overlying said gate oxide layer wherein said first conducting layer comprises a polysilicon layer underlying a tungsten/tungsten nitride layer; depositing said cap nitride layer overlying said first conducting layer; patterning said cap nitride layer and said tungsten/tungsten nitride layer to form a hard mask; thereafter depositing a nitride layer overlying said hard mask and said polysilicon layer wherein said nitride layer protects said tungsten/tungsten nitride layer from oxidation; and thereafter etching away polysilicon layer and said gate oxide layer where they are not covered by said hard mask to form said memory gate in said memory area and said logic gate in said logic area.
Claim 10
Dependent Claim
61 words
The method according to claim 1 before said step of forming said ONO layer, further comprising: depositing a layer of silicon oxide overlying said memory gate, said logic gate, and said logic memory boundary structure; implanting boron ions into said substrate to adjust threshold voltage; and forming lightly doped source/drain (LDD) regions in said logic area and in said memory area.
Claim 11
Dependent Claim
73 words
The method according to claim 9 wherein said step of forming LDD regions further comprises: implanting ions into said substrate to form LDD regions in said logic area; thereafter forming disposable sidewall spacers on said memory gate and said logic memory boundary structure; implanting ions into said memory area using said disposable sidewalls spacers as a mask to form said LDD regions in said memory area; and thereafter removing said disposable sidewall spacers.
Claim 12
Dependent Claim
25 words
The method according to claim 10 wherein said disposable sidewall spacers are chosen from the group consisting of polysilicon, silicon nitride, and borophosphosilicate glass (BPSG).
Claim 13
Dependent Claim
91 words
The method according to claim 1 wherein said first conducting layer comprises polysilicon and wherein said step of forming said ONO layer comprises: using an in-situ steam generation (ISSG) tool to grow a first silicon dioxide layer overlying said substrate, said first conducting layer, said cap nitride layer; depositing a silicon nitride layer overlying said first silicon dioxide layer by treating said first silicon dioxide layer in an NH3 ambient at greater than 850° C.; and growing a second silicon dioxide layer overlying said silicon nitride layer using said ISSG tool.
Claim 14
Dependent Claim
52 words
The method according to claim 12 wherein said first silicon dioxide layer has a thickness of between about 3.0 and 5.0 nm, the silicon nitride layer has a thickness of between about 3 and 6 nm, and the second silicon dioxide layer has a thickness of between about 3 and 8 nm.
Claim 15
Dependent Claim
71 words
The method according to claim 1 before said step of conform ally depositing a polysilicon layer overlying said ONO layer further comprising: etching away the oxide-nitride portion of said ONO layer overlying said substrate using DSW as an etching mask; and forming a third oxide layer overlying a first oxide portion of said ONO layer remaining whereby at least an outside portion of said polysilicon spacers has no nitride layer thereunder.
Claim 16
Dependent Claim
32 words
The method according to claim 1 wherein said polysilicon layer is phosphorus or arsenic doped and is deposited by chemical vapor deposition to a thickness of between about 60 and 100 nm.
Claim 17
Dependent Claim
45 words
The method according to claim 1 further comprising etching back said polysilicon spacers in said memory area until a top surface of said polysilicon spacers is below a top surface of said first conducting layer of said memory gate and said logic memory boundary structure.
Claim 18
Dependent Claim
20 words
The method according to claim 1 further comprising saliciding said logic gate and said source/drain region in said memory area.
Claim 19
Dependent Claim
67 words
The method according to claim 1 further comprising: planarizing said oxide layer to a top surface of said cap nitride layer; removing exposed said cap nitride layer in said memory area to expose said first conducting layer; depositing a second conducting layer overlying said oxide layer and exposed said first conducting layer; and patterning said second conducting layer to form a word gate in said memory area.
Claim 20
Dependent Claim
38 words
The method according to claim 18 wherein said step of planarizing said oxide layer comprises chemical mechanical polishing (CMP) and wherein a dummy nitride pattern is formed in said logic area to prevent dishing during said CMP process.
Claim 21
Dependent Claim
22 words
The method according to claim 18 wherein said second conducting layer is chosen from the group containing polysilicon, tungsten/polysilicon, and tungsten silicon/polysilicon.
Claim 22
Dependent Claim
23 words
The method according to claim 18 wherein said second conducting layer is deposited to a thickness of between about 15 and 20 nm.
Claim 23
Dependent Claim
33 words
The method according to claim 1 further comprising: opening a contact hole through said oxide layer to a source/drain region in said memory area; and filling said contact hole with a tungsten layer.
Claim 24
Dependent Claim
94 words
The method according to claim 22 after said step of saliciding said control gates, further comprising: depositing a silicon nitride layer overlying said substrate and said control gates; depositing a dielectric layer overlying said silicon nitride layer and etching back said dielectric layer to a level of a top surface of said control gates; and repeating the following steps until said control gates are completely covered: depositing a thin silicon nitride layer overlying said control gates and said dielectric layer; and etching back said thin silicon nitride layer to form thin silicon nitride spacers.
Claim 25
Independent Claim
344 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; etching back said polysilicon spacers in said memory area until a top surface of said polysilicon spacers is below a top surface of said first conducting layer of said memory gate and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates, said logic gates, and said source/drain regions; depositing an oxide layer overlying said salicided gates and source/drain regions and planarizing said oxide layer to a top surface of said cap nitride layer; removing exposed said cap nitride layer in said memory area to expose said first conducting layer; depositing a second conducting layer overlying said oxide layer and exposed said first conducting layer; and patterning said second conducting layer to form a word gate in said memory area to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 26
Independent Claim
344 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; etching back said polysilicon spacers in said memory area until a top surface of said polysilicon spacers is below a top surface of said first conducting layer of said memory gate and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates, said logic gates, and said source/drain regions; depositing an oxide layer overlying said salicided gates and source/drain regions and planarizing said oxide layer to a top surface of said cap nitride layer; removing exposed said cap nitride layer in said memory area to expose said first conducting layer; depositing a second conducting layer overlying said oxide layer and exposed said first conducting layer; and patterning said second conducting layer to form a word gate in said memory area to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 27
Dependent Claim
174 words
The method according to claim 24 wherein said step of simultaneously defining a logic gate in said logic area and a memory gate in said memory area comprises: forming said gate oxide layer on said substrate; depositing said first conducting layer overlying said gate oxide layer; forming a first cap oxide layer over said first conducting layer in said logic area; depositing said cap nitride layer overlying said first conducting layer in said memory area and overlying said first cap oxide layer in said logic area; forming a second cap oxide layer overlying said cap nitride layer in said memory area; and patterning said first and second cap oxide layers and said cap nitride layer to form a hard mask wherein said first and second cap oxide layers form said hard mask; and etching away said cap nitride layer, said first conducting layer, and said gate oxide layer where they are not covered by said hard mask to form said memory gate in said memory area and said logic gate in said logic area.
Claim 28
Dependent Claim
21 words
The method according to claim 25 wherein said gate oxide layer has a thickness of between about 2 and 10 nanometers.
Claim 29
Dependent Claim
23 words
The method according to claim 25 wherein said first conducting layer comprises polysilicon having a thickness of between about 150 and 250 nm.
Claim 30
Dependent Claim
21 words
The method according to claim 26 wherein said first and second cap oxide layers have a thickness of about 30 nm.
Claim 31
Dependent Claim
21 words
The method according to claim 25 wherein said cap nitride layer has a thickness of between about 100 and 200 nm.
Claim 32
Dependent Claim
60 words
The method according to claim 25 wherein said step of etching away said cap nitride layer, said first conducting layer, and said gate oxide layer is a reactive on etch wherein the etch rate of nitride is close to the etch rate of polysilicon and wherein the etch rate of oxide is much slower than the etch rate of polysilicon.
Claim 33
Dependent Claim
65 words
The method according to claim 24 before said step of forming said ONO layer, further comprising: depositing a layer of silicon oxide overlying said memory gate, said logic gate, and said logic memory boundary structure; implanting boron ions into said substrate to adjust threshold voltage under said control gate; and forming lightly doped source/drain (LDD) regions in said logic area and in said memory area.
Claim 34
Dependent Claim
73 words
The method according to claim 31 wherein said step of forming LDD regions further comprises: implanting ions into said substrate to form LDD regions in said logic area; thereafter forming disposable sidewall spacers on said memory gate and said logic memory boundary structure; implanting ions into said memory area using said disposable sidewalls spacers as a mask to form said LDD regions in said memory area; and thereafter removing said disposable sidewall spacers.
Claim 35
Dependent Claim
25 words
The method according to claim 32 wherein said disposable sidewall spacers are chosen from the group consisting of polysilicon, silicon nitride, and borophosphosilicate glass (BPSG).
Claim 36
Dependent Claim
91 words
The method according to claim 24 wherein said first conducting layer comprises polysilicon and wherein said step of forming said ONO layer comprises: using an in-situ steam generation (ISSG) tool to grow a first silicon dioxide layer overlying said substrate, said first conducting layer, said cap nitride layer; depositing a silicon nitride layer overlying said first silicon dioxide layer by treating said first silicon dioxide layer in an NH3 ambient at greater than 850° C.; and growing a second silicon dioxide layer overlying said silicon nitride layer using said ISSG tool.
Claim 37
Dependent Claim
52 words
The method according to claim 34 wherein said first silicon dioxide layer has a thickness of between about 3.0 and 5.0 nm, the silicon nitride layer has a thickness of between about 3 and 6 nm, and the second silicon dioxide layer has a thickness of between about 3 and 8 nm.
Claim 38
Dependent Claim
64 words
The method according to claim 24 before said step of conformally depositing a polysilicon layer overlying said ONO layer further comprising: etching away the oxide-nitride portion of said ONO layer overlying said substrate; and forming a third oxide layer overlying a first oxide portion of said ONO layer remaining whereby at least an outside portion of said polysilicon spacers has no nitride layer thereunder.
Claim 39
Dependent Claim
32 words
The method according to claim 24 wherein said polysilicon layer is phosphorus or arsenic doped and is deposited by chemical vapor deposition to a thickness of between about 60 and 100 nm.
Claim 40
Dependent Claim
38 words
The method according to claim 24 wherein said step of planarizing said oxide layer comprises chemical mechanical polishing (CMP) and wherein a dummy nitride pattern is formed in said logic area to prevent dishing during said CMP process.
Claim 41
Dependent Claim
22 words
The method according to claim 24 wherein said second conducting layer is chosen from the group containing polysilicon, tungsten/polysilicon, and tungsten silicon/polysilicon.
Claim 42
Dependent Claim
48 words
The method according to claim 24 wherein said word gate in said memory area is formed by: patterning said second conducting layer and underlying said first conducting layer; and implanting boron ions into said substrate adjacent to said word line to prevent word line to word line leakage.
Claim 43
Dependent Claim
23 words
The method according to claim 24 wherein said second conducting layer is deposited to a thickness of between about 150 and 250 nanometers.
Claim 44
Independent Claim
284 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; forming STI for memory cell isolation and logic active area isolation simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates and said source/drain regions in said logic area; depositing an oxide layer overlying said salicided gates and source/drain regions; opening a contact hole through said oxide layer to a source/drain region in said memory area; and filling said contact hole with a tungsten layer to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 45
Independent Claim
284 words
A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising: providing a substrate having a memory area and a logic area; forming STI for memory cell isolation and logic active area isolation simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer; forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure; conformally depositing a polysilicon layer overlying said ONO layer; etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area; forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask; thereafter removing said polysilicon spacers in said logic area; forming source/drain regions in said memory area using said control gates as an implantation mask; saliciding said control gates and said source/drain regions in said logic area; depositing an oxide layer overlying said salicided gates and source/drain regions; opening a contact hole through said oxide layer to a source/drain region in said memory area; and filling said contact hole with a tungsten layer to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.
Claim 46
Dependent Claim
146 words
The method according to claim 42 wherein said step of simultaneously defining a logic gate in sad logic area and a memory gate in said memory area comprises: forming said gate oxide layer on said substrate; depositing said first conducting layer overlying said gate oxide layer wherein said first conducting layer comprises a polysilicon layer underlying a tungsten/tungsten nitride layer; depositing said cap nitride layer overlying said first conducting layer; patterning said cap nitride layer and said tungsten/tungsten nitride layer to form a hard mask; thereafter depositing a nitride layer overlying said hard mask and said polysilicon layer wherein said nitride layer protects said tungsten/tungsten nitride layer from oxidation; and thereafter etching away polysilicon layer and said gate oxide layer where they are not covered by said hard mask to form said memory gate in said memory area and said logic gate in said logic area.
Claim 47
Dependent Claim
21 words
The method according to claim 42 wherein said gate oxide layer has a thickness of between about 2 and 10 nanometers.
Claim 48
Dependent Claim
20 words
The method according to claim 43 wherein said polysilicon layer has a thickness of between about 150 and 250 nm.
Claim 49
Dependent Claim
21 words
The method according to claim 42 wherein said cap nitride layer has a thickness of between about 100 and 200 nm.
Claim 50
Dependent Claim
65 words
The method according to claim 42 before said step of forming said ONO layer, further comprising: depositing a layer of silicon oxide overlying said memory gate, said logic gate, and said logic memory boundary structure; implanting boron ions into said substrate to adjust threshold voltage under said control gate; and forming lightly doped source/drain (LDD) regions in said logic area and in said memory area.
Claim 51
Dependent Claim
73 words
The method according to claim 42 wherein said step of forming LDD regions further comprises: implanting ions into said substrate to form LDD regions in said logic area; thereafter forming disposable sidewall spacers on said memory gate and said logic memory boundary structure; implanting ions into said memory area using said disposable sidewalls spacers as a mask to form said LDD regions in said memory area; and thereafter removing said disposable sidewall spacers.
Claim 52
Dependent Claim
25 words
The method according to claim 48 wherein said disposable sidewall spacers are chosen from the group consisting of polysilicon, silicon nitride, and borophosphosilicate glass (BPSG).
Claim 53
Dependent Claim
84 words
The method according to claim 42 wherein said step of forming said ONO layer comprises: using an in-situ steam generation (ISSG) tool to grow a first silicon dioxide layer overlying said substrate, said first conducting layer, said cap nitride layer; depositing a silicon nitride layer overlying said first silicon dioxide layer by treating said first silicon dioxide layer in an NH 3 ambient at greater than 850° C.; and growing a second silicon dioxide layer overlying said silicon nitride layer using said ISSG tool.
Claim 54
Dependent Claim
52 words
The method according to claim 50 wherein said first silicon dioxide layer has a thickness of between about 3.0 and 5.0 nm, the silicon nitride layer has a thickness of between about 3 and 6 nm, and the second silicon dioxide layer has a thickness of between about 3 and 8 nm.
Claim 55
Dependent Claim
64 words
The method according to claim 42 before said step of conformally depositing a polysilicon layer overlying said ONO layer further comprising: etching away the oxide-nitride portion of said ONO layer overlying said substrate; and forming a third oxide layer overlying a first oxide portion of said ONO layer remaining whereby at least an outside portion of said polysilicon spacers has no nitride layer thereunder.
Claim 56
Dependent Claim
32 words
The method according to claim 42 wherein said polysilicon layer is phosphrus or arsenic doped and is deposited by chemical vapor deposition to a thickness of between about 60 and 100 nm.
Claim 57
Dependent Claim
94 words
The method according to claim 42 after said step of saliciding said control gates, further comprising: depositing a silicon nitride layer overlying said substrate and said control gates; depositing a dielectric layer overlying said silicon nitride layer and etching back said dielectric layer to a level of a top surface of said control gates; and repeating the following steps until said control gates are completely covered: depositing a thin silicon nitride layer overlying said control gates and said dielectric layer; and etching back said thin silicon nitride layer to form thin silicon nitride spacers.
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