US6556490B2
Expired / Lapsed
US
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System and method for redundancy implementation in a semiconductor device
Assignee: Synopsys Inc
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Filing: 2002-03-15
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Granted: 2003-04-29
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Expires: 2022-03-15
Abstract
Abstract A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.
Inventors
- 👤 Alex Shubat
- 👤 Chang Hee Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:01
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/848; G11C29/80; G11C29/802; G11C29/785
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
121 words
An integrated semiconductor device, comprising: at least one memory instance having a prime memory array and a redundant memory portion; fuse box means disposed external to said at least one memory instance in a selected area of said integrated semiconductor device, said fuse box means for storing location information pertaining to a faulty portion in said prime memory array; storage means disposed in said at least one memory instance for receiving said location information from said fuse box means; means for transferring said location information to said storage means; and means for replacing at least a part of said faulty portion in said prime memory array with at least a part of said redundant memory portion based on said location information.
Claim 2
Dependent Claim
121 words
An integrated semiconductor device, comprising: at least one memory instance having a prime memory array and a redundant memory portion; fuse box means disposed external to said at least one memory instance in a selected area of said integrated semiconductor device, said fuse box means for storing location information pertaining to a faulty portion in said prime memory array; storage means disposed in said at least one memory instance for receiving said location information from said fuse box means; means for transferring said location information to said storage means; and means for replacing at least a part of said faulty portion in said prime memory array with at least a part of said redundant memory portion based on said location information.
Claim 3
Dependent Claim
21 words
The integrated semiconductor device as set forth in claim 1 , wherein said faulty portion includes at least one faulty wordline.
Claim 4
Dependent Claim
21 words
The integrated semiconductor device as set forth in claim 1 , wherein said faulty portion includes at least one faulty bitline.
Claim 5
Dependent Claim
29 words
The integrated semiconductor device as set forth in claim 1 , wherein said faulty portion includes at least one faulty column block of said at least one memory instance.
Claim 6
Dependent Claim
26 words
The integrated semiconductor device as set forth in claim 1 , wherein said at least one memory instance comprises a Dynamic Random Access Memory (DRAM) circuit.
Claim 7
Dependent Claim
26 words
The integrated semiconductor device as set forth in claim 1 , wherein said at least one memory instance comprises a Static Random Access Memory (SRAM) circuit.
Claim 8
Dependent Claim
27 words
The integrated semiconductor device as set forth in claim 1 , wherein said at least one memory instance comprises a an Electrically Programmable Read-Only Memory (EPROM) circuit.
Claim 9
Dependent Claim
23 words
The integrated semiconductor device as set forth in claim 1 , wherein said at least one memory instance comprises a Flash EPROM circuit.
Claim 10
Dependent Claim
110 words
A memory compiler for designing an integrated semiconductor device with redundancy, comprising: a memory macro cell associated with at least one memory instance that includes a prime memory array and a redundant memory portion; a fuse box register disposed external to said memory macro cell, said fuse box register for storing location information relating to a faulty portion in said prime memory array; and storage means disposed in said at least one memory instance for receiving said location information from said fuse box register, wherein said location information is used for replacing at least a part of said faulty portion with at least a part of said redundant memory portion.
Claim 11
Dependent Claim
110 words
A memory compiler for designing an integrated semiconductor device with redundancy, comprising: a memory macro cell associated with at least one memory instance that includes a prime memory array and a redundant memory portion; a fuse box register disposed external to said memory macro cell, said fuse box register for storing location information relating to a faulty portion in said prime memory array; and storage means disposed in said at least one memory instance for receiving said location information from said fuse box register, wherein said location information is used for replacing at least a part of said faulty portion with at least a part of said redundant memory portion.
Claim 12
Dependent Claim
28 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said faulty portion includes at least one faulty wordline.
Claim 13
Dependent Claim
28 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said faulty portion includes at least one faulty bitline.
Claim 14
Dependent Claim
29 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said faulty portion includes at least one faulty column block.
Claim 15
Dependent Claim
33 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said at least one memory instance comprises a Dynamic Random Access Memory (DRAM) circuit.
Claim 16
Dependent Claim
33 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said at least one memory instance comprises a Static Random Access Memory (SRAM) circuit.
Claim 17
Dependent Claim
34 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said at least one memory instance comprises a an Electrically Programmable Read-Only Memory (EPROM) circuit.
Claim 18
Dependent Claim
30 words
The memory compiler for designing an integrated semiconductor device with redundancy as set forth in claim 9 , wherein said at least one memory instance comprises a Flash EPROM circuit.
Claim 19
Independent Claim
92 words
A method of effectuating redundancy in an embedded memory circuit having a main memory area and a redundant memory portion, comprising the steps: storing location information in a fuse area outside said embedded memory circuit, said location information pertaining to a faulty portion in said main memory area; transferring said location information to a redundancy scan storage element in said memory circuit; and replacing at least a part of said faulty portion in said main memory area with at least a part of said redundant memory portion based on said location information.
Claim 20
Independent Claim
92 words
A method of effectuating redundancy in an embedded memory circuit having a main memory area and a redundant memory portion, comprising the steps: storing location information in a fuse area outside said embedded memory circuit, said location information pertaining to a faulty portion in said main memory area; transferring said location information to a redundancy scan storage element in said memory circuit; and replacing at least a part of said faulty portion in said main memory area with at least a part of said redundant memory portion based on said location information.
Claim 21
Dependent Claim
30 words
The method of effectuating redundancy in an embedded memory circuit as set forth in claim 17 , wherein said location information is determined based on testing said main memory area.
Claim 22
Dependent Claim
38 words
The method of effectuating redundancy in an embedded memory circuit as set forth in claim 17 , wherein said location information is transferred from said fuse area to said redundancy scan storage element upon resetting said memory circuit.
Claim 23
Dependent Claim
37 words
The method of effectuating redundancy in an embedded memory circuit as set forth in claim 17 , further including the step of testing said redundant memory portion before said location information is stored in said fuse area.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-28 | 2006-10-28 | 2007-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-28 | 2010-10-28 | 2011-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-28 | 2014-10-28 | 2015-04-29 | $7700.00 | Window Closed / Lapsed |