Semiconductor memory device

Claim 2

A semiconductor memory device comprising a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit, wherein: the semiconductor memory device has a first refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal input externally and a refresh address generated from the first internal address generation circuit that operates in response to the periodic pulse signal input externally, and a second refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and a refresh address generated from the second internal address generation circuit, and different memory regions are refreshed in the first refresh mode versus the second refresh mode.

Claim 3

The semiconductor memory device according to claim 1 , wherein a refresh address generated from the first internal address generation circuit is used for refreshing the entire memory region and a refresh address generated from the second internal address generation circuit is used for refreshing only the memory cells in a specific part of the memory region.

Claim 4

The semiconductor memory device according to claim 1 , wherein the first internal address generation circuit and the second internal address generation circuit comprise respective counters and the refresh regions are changed depending upon the number of bits of each of the counter.

Claim 5

The semiconductor memory device according to claim 1 , wherein the second internal address generation circuit comprises a counter, a comparison circuit and an adder, wherein output data of the counter are input as one input signal of the comparison circuit and as one input signal of the adder, and respective data, which are preset and fixed to “H” or “L”, are input as the other input signal of the comparison circuit and as the other input signal of the adder, thereby enabling successive arbitrary addresses to be set.

Claim 6

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to the output signal from the timer circuit, wherein: the semiconductor memory device has a first refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal input externally and a refresh address generated from the first internal address generation circuit that operates in response to the periodic pulse signal input externally, a second refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and a refresh address generated from the first internal address generation circuit that operates in response to the internally generated pulse signal, and a third refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and the refresh address generated from the second internal address generation circuit, and in the first refresh mode and the second refresh mode, the same memory region is refreshed, and in the third refresh mode, a memory region that is different from the memory regions that are refreshed by the first and the second refresh modes is refreshed.

Claim 7

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to the output signal from the timer circuit, wherein: the semiconductor memory device has a first refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal input externally and a refresh address generated from the first internal address generation circuit that operates in response to the periodic pulse signal input externally, a second refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and a refresh address generated from the first internal address generation circuit that operates in response to the internally generated pulse signal, and a third refresh mode for refreshing data stored in the memory cell by using a periodic pulse signal generated from the timer circuit and the refresh address generated from the second internal address generation circuit, and in the first refresh mode and the second refresh mode, the same memory region is refreshed, and in the third refresh mode, a memory region that is different from the memory regions that are refreshed by the first and the second refresh modes is refreshed.

Claim 8

The semiconductor memory device according to claim 5 , wherein the refresh address generated from the first internal address generation circuit is used for the refresh of the entire memory region and the refresh address generated from the second address generation circuit is used for refresh of only memory cells of a part of the memory region.

Claim 9

The semiconductor memory device according to claim 5 , wherein the timer circuit is capable of changing the period of the periodic pulse, and when the refresh is carried out by using the output signal of the timer circuit, the period of the periodic pulse output from the timer circuit is varied between the case where the address generated from the first internal address generation circuit is used and the case where the address generated from the second internal address generation circuit is used, thereby changing the period of the refresh.

Claim 10

The semiconductor memory device according to claim 7 , wherein a fuse is employed for the timer circuit, thereby enabling the period of the periodic pulse signal output from the timer circuit to be changed.

Claim 11

The semiconductor memory device according to claim 5 , wherein the first internal address generation circuit and the second internal address generation circuit comprise respective counters and the refresh regions are changed depending upon the number of bits of each of the counter.

Claim 12

The semiconductor memory device according to claim 5 , wherein the second internal address generation circuit comprises a counter, a comparison circuit and an adder, wherein output data of the counter are input as one input signal of the comparison circuit and as one input signal of the adder, and respective data, which are preset and fixed to “H” or “L”, are input as the other input signal of the comparison circuit and as the other input signal of the adder, thereby enabling successive arbitrary addresses to be set.

Claim 13

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells requiring refresh, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and an internal address generation circuit having a counter and a decode circuit, which operates in response to a periodic pulse signal input externally or the output signal from the timer circuit, so as to generate a refresh address; wherein the semiconductor memory device operates refreshing by using the periodic pulse signal input externally or the periodic pulse signal generated from the timer circuit and a refresh address generated from the internal address generation circuit, and the internal address generation circuit generates different addresses between the case where the refresh is carried out by using the periodic pulse signal input externally and the case where the refresh is carried out by using the refresh address generated from the internal address generation circuit, thereby enabling different memory regions to be refreshed.

Claim 14

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells requiring refresh, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and an internal address generation circuit having a counter and a decode circuit, which operates in response to a periodic pulse signal input externally or the output signal from the timer circuit, so as to generate a refresh address; wherein the semiconductor memory device operates refreshing by using the periodic pulse signal input externally or the periodic pulse signal generated from the timer circuit and a refresh address generated from the internal address generation circuit, and the internal address generation circuit generates different addresses between the case where the refresh is carried out by using the periodic pulse signal input externally and the case where the refresh is carried out by using the refresh address generated from the internal address generation circuit, thereby enabling different memory regions to be refreshed.