Patent US6687147B2 successfully refreshed from Google Patents.
US6687147B2
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Cubic memory array with diagonal select lines
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 2002-07-23
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Granted: 2004-02-03
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Expires: 2022-07-23
Abstract
Abstract A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
Inventors
- 👤 Peter Fricke
- 👤 Andrew L. Van Brocklin
- 👤 Andrew Koll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:26
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; H; H10; H10D; H10D88/00; G11C5/025; G11C7/00; G11C7/18; H10B; H10B99/00; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/01
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
105 words
A cubic memory array, comprising: a plurality of memory cells arranged in arrays with rows and columns, said arrays being layered on a substrate; a plurality of conductive pillars, each conductive pillar being connected to a plurality of said memory cells and extending between layers of memory cells; a first plurality of select lines that are each connected to a plurality of said memory cells in a row; and a second plurality of select lines that are each connected to a plurality of said conductive pillars and are divided into first and second groups; wherein said first group is arranged diagonally among said conductive pillars.
Claim 2
Dependent Claim
105 words
A cubic memory array, comprising: a plurality of memory cells arranged in arrays with rows and columns, said arrays being layered on a substrate; a plurality of conductive pillars, each conductive pillar being connected to a plurality of said memory cells and extending between layers of memory cells; a first plurality of select lines that are each connected to a plurality of said memory cells in a row; and a second plurality of select lines that are each connected to a plurality of said conductive pillars and are divided into first and second groups; wherein said first group is arranged diagonally among said conductive pillars.
Claim 3
Dependent Claim
30 words
The cubic memory array of claim 1 , wherein each of said second plurality of select lines is connected to every other pillar along a length of that select line.
Claim 4
Dependent Claim
35 words
The cubic memory array of claim 1 , further comprising control circuitry formed around a periphery of said cubic memory array, said control circuit selectively effecting reading and writing of data to said memory cells.
Claim 5
Dependent Claim
23 words
The cubic memory array of claim 3 , wherein said control circuitry comprises a switching element electrically connected to at least one pillar.
Claim 6
Dependent Claim
36 words
The cubic memory array of claim 3 , wherein a single switching element in said control circuitry simultaneously accesses and controls a plurality of select lines from both said first and second pluralities of select lines.
Claim 7
Dependent Claim
27 words
The cubic memory array of claim 3 , wherein said control circuitry may simultaneously drive a plurality of said pillars that are connected to different select lines.
Claim 8
Dependent Claim
25 words
The cubic memory array of claim 1 , wherein a first layer of said memory cells is formed directly on a surface of said substrate.
Claim 9
Dependent Claim
28 words
The cubic memory array of claim 1 , further comprising circuitry formed on said substrate under said memory cells, pillars and select lines of said cubic memory array.
Claim 10
Dependent Claim
34 words
The cubic memory array of claim 1 , wherein select lines of said first group are arranged diagonally at a 45 degree angle with respect to said rows and columns of said memory cells.
Claim 11
Independent Claim
120 words
A method of creating a memory circuit, comprising: forming a first plurality of select-lines in a plane substantially parallel to a substrate; forming a second plurality of select-lines in a plane substantially parallel to said substrate, said second plurality of select-lines being divided into first and second groups, wherein said first group is formed in a direction normal to that of said first plurality of select-lines, and said second group is formed in a direction substantially diagonal to that of said first group; forming a plurality of pillars normal to said substrate; and forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
Claim 12
Independent Claim
120 words
A method of creating a memory circuit, comprising: forming a first plurality of select-lines in a plane substantially parallel to a substrate; forming a second plurality of select-lines in a plane substantially parallel to said substrate, said second plurality of select-lines being divided into first and second groups, wherein said first group is formed in a direction normal to that of said first plurality of select-lines, and said second group is formed in a direction substantially diagonal to that of said first group; forming a plurality of pillars normal to said substrate; and forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
Claim 13
Dependent Claim
29 words
The method of claim 10 , further comprising electrically connecting each of said second plurality of select lines to every other pillar along a length of that select line.
Claim 14
Dependent Claim
24 words
The method of claim 10 , further comprising forming another layer of memory cells, disposed in an array, on said array of memory cells.
Claim 15
Dependent Claim
33 words
The method of claim 10 , further comprising forming control circuitry around a periphery of said cubic memory array, said control circuit selectively effecting reading and writing of data to said memory cells.
Claim 16
Dependent Claim
24 words
The method of claim 13 , wherein said forming said control circuitry comprises forming a switching element electrically connected to at least one pillar.
Claim 17
Dependent Claim
25 words
The method of claim 10 , further forming circuitry on said substrate under said memory cells, pillars and select lines of said cubic memory array.
Claim 18
Dependent Claim
20 words
The method of claim 10 , further comprising forming said memory circuit on an existing circuit formed on said substrate.
Claim 19
Dependent Claim
23 words
The method of claim 10 , further comprising forming a first layer of said memory cells directly on a surface of said substrate.
Claim 20
Dependent Claim
50 words
A cubic memory array, comprising: storage means for storing digital data; and control means for reading and writing digital data in said storage means, said control means comprising a plurality of selection lines connected to memory cells in said storage means; and means for reducing cross-coupling between said selection lines.
Claim 21
Dependent Claim
50 words
A cubic memory array, comprising: storage means for storing digital data; and control means for reading and writing digital data in said storage means, said control means comprising a plurality of selection lines connected to memory cells in said storage means; and means for reducing cross-coupling between said selection lines.
Claim 22
Dependent Claim
27 words
The cubic memory array of claim 18 , said control means further comprise a plurality of conductive pillars connected to said selection lines and said memory cells.
Claim 23
Dependent Claim
44 words
The cubic memory array of claim 19 , wherein said means for reducing cross-coupling between said selection lines comprises disposing a first group of said selection lines above said conductive pillars and disposing a second group of said selection lines below said conductive pillars.
Claim 24
Dependent Claim
27 words
The cubic memory array of claim 18 , said control means further comprise means for controlling a plurality of said selection lines with a single control element.
Claim 25
Dependent Claim
20 words
The cubic memory array of claim 18 , wherein said control means access a plurality of said memory cells simultaneously.
Claim 26
Dependent Claim
36 words
The cubic memory array of claim 18 , wherein said means for reducing cross-coupling between said selection lines comprises disposing a first group of said selection lines diagonal to a second group of said selection lines.
References Cited (Backward Citations)
US5684981A
Cited
US6004825A
Cited
US5835396A
Cited
US6418063B1
Cited
US6166986A
Cited
US6373741B2
Cited
US6411557B2
Cited
US6424553B2
Cited
US6400642B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-02-02 | 2007-08-04 | 2008-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-02-02 | 2011-08-04 | 2012-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-02-02 | 2015-08-04 | 2016-02-03 | $7700.00 | Window Closed / Lapsed |