US6411557B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory architecture with single-port cell and dual-port (read and write) functionality
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-02-02
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Granted: 2002-06-25
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Expires: 2021-02-02
Abstract
Abstract A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e., the READ operation); globally selecting the second memory location; concurrently with the globally selecting, globally sensing the first datum at the first memory location; outputting the first data subsequent to the globally sensing; inputting the second datum substantially immediately subsequent to the outputting the first datum; locally selecting the second memory location; and storing the second datum (i.e., WRITE operation). Also, a WRITE-AFTER-WRITE operation similarly is accomplished by interposing a PRECHARGE operation between subsequent WRITE operations. A redundant group of memory cells, and techniques for assigning them to a memory location in a “FAULT” condition, also are provided.
Inventors
- 👤 Esin Terzioglu
- 👤 Morteza Cyrus Afghahi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:49
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
227 words
A memory redundancy circuit in single-port hierarchical memory structure having a predetermined memory access speed and a memory access period, comprising: a. a memory module having (1) memory cells disposed to store data, the memory cells including a designated group of memory cells being assigned to represent a logical portion of the memory structure and a redundant group of memory cells; (2) hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; (3) hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; (4) a redundancy controller coupled with the designated group and the redundant group, the redundancy controller assigning the redundant group to the logical portion of the memory structure, responsive to a preselected memory group condition, and providing redundancy thereby; b. hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifiers of selected memory modules; c. hierarchically-coupled local and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.
Claim 2
Dependent Claim
227 words
A memory redundancy circuit in single-port hierarchical memory structure having a predetermined memory access speed and a memory access period, comprising: a. a memory module having (1) memory cells disposed to store data, the memory cells including a designated group of memory cells being assigned to represent a logical portion of the memory structure and a redundant group of memory cells; (2) hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; (3) hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; (4) a redundancy controller coupled with the designated group and the redundant group, the redundancy controller assigning the redundant group to the logical portion of the memory structure, responsive to a preselected memory group condition, and providing redundancy thereby; b. hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifiers of selected memory modules; c. hierarchically-coupled local and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.
Claim 3
Dependent Claim
28 words
The memory redundancy circuit of claim 1 , wherein the redundancy controller comprises a redundancy decoder responsive to an encoded signal representative of the preselected memory group condition.
Claim 4
Dependent Claim
30 words
The memory redundancy circuit of claim 2 , wherein the redundancy controller further comprises a plurality of selectable switches, the plurality of selectable switches encoding the preselected memory group condition.
Claim 5
Dependent Claim
16 words
The memory redundancy circuit of claim 3 , wherein the plurality of selectable switches are fuses.
Claim 6
Dependent Claim
26 words
The memory redundancy circuit of claim 4 , wherein the preselected memory group condition is a “FAILED” memory group condition, representative of a designated group malfunction.
Claim 7
Dependent Claim
54 words
The memory redundancy circuit of claim 1 , wherein each of the designated group of memory cells and the redundant group of memory cells comprises one of a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, and a combination thereof.
Claim 8
Dependent Claim
226 words
In a single-port hierarchical memory structure having local and global data sensing, local and global location selecting, and hierarchically-coupled memory modules having redundant groups of memory cells and a redundant memory location, wherein storage of a second datum at a designated memory location is to follow sensing of a first datum at the designated memory location, and wherein the designated memory location develops a “FAILED” condition, a method for substantially simultaneously retrieving a first datum from the designated memory location in the memory module and storing the second datum in the redundant memory location, the method comprising: a. locally selecting the designated memory location from which the first datum is to be retrieved; b. locally sensing the first datum in the designated memory location (READ operation); c. detecting the “FAILED” condition in the designated memory location; d. assigning the redundant memory location to represent the designated memory location; e. globally selecting the redundant memory location for storing the second datum; f. substantially concurrently with the globally selecting, globally sensing the first datum in the designated memory location; g. outputting the first datum subsequent to the globally sensing; h. inputting the second datum substantially immediately subsequent to the outputting the first datum; i. locally selecting the redundant memory location for storing the second datum; and j. storing the second datum in the redundant memory location (WRITE operation).
Claim 9
Dependent Claim
226 words
In a single-port hierarchical memory structure having local and global data sensing, local and global location selecting, and hierarchically-coupled memory modules having redundant groups of memory cells and a redundant memory location, wherein storage of a second datum at a designated memory location is to follow sensing of a first datum at the designated memory location, and wherein the designated memory location develops a “FAILED” condition, a method for substantially simultaneously retrieving a first datum from the designated memory location in the memory module and storing the second datum in the redundant memory location, the method comprising: a. locally selecting the designated memory location from which the first datum is to be retrieved; b. locally sensing the first datum in the designated memory location (READ operation); c. detecting the “FAILED” condition in the designated memory location; d. assigning the redundant memory location to represent the designated memory location; e. globally selecting the redundant memory location for storing the second datum; f. substantially concurrently with the globally selecting, globally sensing the first datum in the designated memory location; g. outputting the first datum subsequent to the globally sensing; h. inputting the second datum substantially immediately subsequent to the outputting the first datum; i. locally selecting the redundant memory location for storing the second datum; and j. storing the second datum in the redundant memory location (WRITE operation).
Claim 10
Dependent Claim
24 words
The method of claim 7 , further comprising precharging bitlines coupled with the memory location, prior to locally sensing the first datum (PRECHARGE operation).
Claim 11
Dependent Claim
22 words
The method of claim 8 , wherein (a) through (j) (PRECHARGE-READ-WRITE operation) are completed within one access cycle of the memory structure.
Claim 12
Dependent Claim
22 words
The method of claim 9 , wherein a plurality of PRECHARGE-READ-WRITE operations are completed within one access cycle of the memory structure.
Claim 13
Independent Claim
147 words
A method for substantially simultaneously retrieving a first datum from a first memory location and storing a second datum in a second memory location, wherein both locations are disposed within a single-port hierarchical memory structure having local and global data sensing, and local and global location selecting, the method comprising: a. locally selecting the first memory location from which the first datum is to be retrieved; b. locally sensing the first datum (READ operation) in the first memory location; c. globally selecting the second memory location; d. substantially concurrently with the globally selecting, globally sensing the first datum at the first memory location; e. outputting the first data subsequent to the globally sensing; f. inputting the second datum substantially immediately subsequent to the outputting the first datum; g. locally selecting the second memory location; and h. storing the second datum (WRITE operation) in the second memory location.
Claim 14
Independent Claim
147 words
A method for substantially simultaneously retrieving a first datum from a first memory location and storing a second datum in a second memory location, wherein both locations are disposed within a single-port hierarchical memory structure having local and global data sensing, and local and global location selecting, the method comprising: a. locally selecting the first memory location from which the first datum is to be retrieved; b. locally sensing the first datum (READ operation) in the first memory location; c. globally selecting the second memory location; d. substantially concurrently with the globally selecting, globally sensing the first datum at the first memory location; e. outputting the first data subsequent to the globally sensing; f. inputting the second datum substantially immediately subsequent to the outputting the first datum; g. locally selecting the second memory location; and h. storing the second datum (WRITE operation) in the second memory location.
Claim 15
Dependent Claim
28 words
The method of claim 11 , further comprising precharging bitlines coupled with the first and the second memory locations, prior to locally sensing the first datum (PRECHARGE operation).
Claim 16
Dependent Claim
22 words
The method of claim 12 , wherein (a) through (h) (PRECHARGE-READ-WRITE operation) are completed within one access cycle of the memory structure.
Claim 17
Dependent Claim
22 words
The method of claim 13 , wherein a plurality of PRECHARGE-READ-WRITE operations are completed within one access cycle of the memory structure.
Claim 18
Dependent Claim
19 words
The method of claim 11 , wherein the first memory location is the same as the second memory location.
Claim 19
Independent Claim
176 words
A method for providing sequential storage of a first datum in a first hierarchical memory structure location and a second datum in a second hierarchical memory structure location within one access cycle of the memory structure, the structure having local and global location selecting, the method comprising: a. globally selecting the first hierarchical memory structure location to which the first datum is to be stored; b. precharging bitlines coupled with the memory cells at the first hierarchical memory structure location (PRECHARGE 1 operation); c. locally selecting the first hierarchical memory structure location; d. storing the first datum (WRITE 1 operation) in the first hierarchical memory structure location; e. globally selecting the second hierarchical memory structure location to which the second datum is to be stored; f. substantially concurrently with the globally selecting the second hierarchical memory structure location, precharging bitlines coupled with the second hierarchical memory structure location (PRECHARGE 2 operation); g. locally selecting the second hierarchical memory structure location; and h. storing the second datum (WRITE 2 operation) in the second hierarchical memory structure location.
Claim 20
Independent Claim
176 words
A method for providing sequential storage of a first datum in a first hierarchical memory structure location and a second datum in a second hierarchical memory structure location within one access cycle of the memory structure, the structure having local and global location selecting, the method comprising: a. globally selecting the first hierarchical memory structure location to which the first datum is to be stored; b. precharging bitlines coupled with the memory cells at the first hierarchical memory structure location (PRECHARGE 1 operation); c. locally selecting the first hierarchical memory structure location; d. storing the first datum (WRITE 1 operation) in the first hierarchical memory structure location; e. globally selecting the second hierarchical memory structure location to which the second datum is to be stored; f. substantially concurrently with the globally selecting the second hierarchical memory structure location, precharging bitlines coupled with the second hierarchical memory structure location (PRECHARGE 2 operation); g. locally selecting the second hierarchical memory structure location; and h. storing the second datum (WRITE 2 operation) in the second hierarchical memory structure location.
Claim 21
Dependent Claim
22 words
The method of claim 16 , wherein (a) through (h) (WRITE-PRECHARGE-WRITE operation) are completed within one access cycle of the memory structure.
Claim 22
Dependent Claim
22 words
The method of claim 17 , wherein a plurality of WRITE-PRECHARGE-WRITE operations are completed within one access cycle of the memory structure.
Claim 23
Dependent Claim
23 words
The method of claim 16 , wherein the first hierarchical memory structure location is the same as the second hierarchical memory structure location.
Claim 24
Dependent Claim
156 words
A single-port hierarchical memory structure having a predetermined memory access speed and a memory access period, comprising: a. memory modules having (1) memory cells disposed to store data; (2) hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; and (3) hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; b. hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifier of selected memory modules; c. hierarchically-coupled local, and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.
Claim 25
Dependent Claim
156 words
A single-port hierarchical memory structure having a predetermined memory access speed and a memory access period, comprising: a. memory modules having (1) memory cells disposed to store data; (2) hierarchically-coupled local and global sense amplifiers, the local sense amplifiers being coupled with the memory cells; and (3) hierarchically-coupled local and global row decoders, the local row decoders being coupled with the memory cells; b. hierarchically-coupled local and global sense amplifiers, selected local sense amplifiers being the global sense amplifier of selected memory modules; c. hierarchically-coupled local, and global row decoders, selected local row decoders being the global row decoders of selected memory modules; and d. a predecoding circuit coupled with selected global row decoders, wherein the predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory structure access speed, and allowing access to a selected memory cell at least twice during the memory access period, thereby providing dual-port functionality thereby.
Claim 26
Dependent Claim
52 words
The single-port hierarchical memory structure of claim 20 , wherein the predecoding circuit is disposed to provide predecoding at a speed more than twice the predetermined memory structure access speed, and allowing access to a selected memory cell three or more times during the memory access period, thereby providing multi-port functionality thereby.
Claim 27
Dependent Claim
144 words
A memory redundancy circuit in a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, the memory redundancy circuit, comprising: a. a redundant group of memory cells; b. a redundancy controller coupled with the designated group and the redundant group, the redundancy controller assigning the redundant group to the logical portion of the memory structure, responsive to a preselected memory group condition; c. a signal input; d. a first memory output coupled with a first memory cell group; e. a second memory output coupled with a second memory cell group; and f. a selector coupled between the signal input, the first memory output, and the second memory output, wherein the decoder decodes the first memory cell group, and being disposed to select and decode the second memory cell group responsive to a group-select signal.
Claim 28
Dependent Claim
144 words
A memory redundancy circuit in a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, the memory redundancy circuit, comprising: a. a redundant group of memory cells; b. a redundancy controller coupled with the designated group and the redundant group, the redundancy controller assigning the redundant group to the logical portion of the memory structure, responsive to a preselected memory group condition; c. a signal input; d. a first memory output coupled with a first memory cell group; e. a second memory output coupled with a second memory cell group; and f. a selector coupled between the signal input, the first memory output, and the second memory output, wherein the decoder decodes the first memory cell group, and being disposed to select and decode the second memory cell group responsive to a group-select signal.
Claim 29
Dependent Claim
40 words
The memory redundancy circuit of claim 22 , wherein the selector comprises a multiplexer, the multiplexer selecting to decode from one of the first memory cell group and the second memory cell, the multiplexer being responsive to the group-select signal.
Claim 30
Dependent Claim
54 words
The memory redundancy circuit of claim 22 , wherein the decoder is a row decoder disposed in a memory module having a plurality of adjacent memory rows, and wherein a first memory row and a second memory row are adjacent memory rows in the memory module, and the group-select signal is an alternative-row-select signal.
Claim 31
Dependent Claim
54 words
The memory redundancy circuit of claim 22 , wherein the decoder is a column decoder disposed in a memory module having a plurality of adjacent memory columns, and wherein a first memory column and a second memory column are adjacent memory columns in the memory module, and the group-select signal is an alternative-column-select signal.
Claim 32
Dependent Claim
57 words
The memory redundancy circuit of claim 22 , wherein the decoder is a row decoder disposed in a memory module having assigned memory rows and a redundant memory row, and wherein a first memory row is an assigned memory row, a second memory row is the redundant memory row and the group-select signal is a redundant-row-select signal.
Claim 33
Dependent Claim
57 words
The memory redundancy circuit of claim 22 , wherein the decoder is a column decoder disposed in a memory module having assigned memory columns and a redundant memory column, and wherein a first memory column is an assigned memory column, a second memory column is the redundant memory column and the group-select signal is a redundant-column-select signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-24 | 2005-12-24 | 2006-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-24 | 2009-12-24 | 2010-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-24 | 2013-12-24 | 2014-06-25 | $7700.00 | Window Closed / Lapsed |