Non-volatile semiconductor memory device and method of driving the same

Claim 1

A non-volatile semiconductor memory device comprising: a memory cell array region in which are arranged a plurality of memory cells at least in a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; a plurality of bit lines extending in a column direction, each of the bit lines being connected to a connect line which connects a pair of memory cells adjacent to each other in the row direction; a plurality of first select gates, each of which is connected to one of the bit lines; and a plurality of I/O lines, each of which is provided for each 2 N (N is an integer of 2 or more) first select gates and connected in common to 2 N bit lines through 2 N first select gates, wherein the memory cell array region is divided into a plurality of block regions in the row direction corresponding to the I/O lines, each of the block regions including 2 N memory cells in the row direction; and wherein a second select gate is provided between one of the I/O lines corresponding to the i-th block region (i is an integer) and one of the bit lines, the bit line being located at a boundary between the block regions and connected to the connect line connecting two of the memory cells respectively disposed in the i-th and (i+1)th block regions that are adjacent to each other in the row direction in the block regions.

Claim 11

A method of driving a non-volatile semiconductor memory device comprising: providing a non-volatile semiconductor memory device which has: a memory cell array region in which are arranged a plurality of memory cells at least in a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; a plurality of bit lines extending in a column direction, each of the bit lines being connected to a connect line which connects two of the memory cells adjacent to each other in the row direction; a word line which is connected to the word gates of the memory cells arranged in the row direction; and a plurality of control gate lines each of which is connected to the first and second control gates respectively provided in adjacent two memory cells with the connect line interposed, the memory cell array region being divided into a plurality of block regions in the row direction corresponding to the I/O lines, and each of the block regions including 2 N memory cells; and performing a data reading or programming operation for one of the first and second non-volatile memory elements in the i-th memory cell in the row direction by using the word line, four of the bit lines, and four of the control gate lines connected to the (i−1)th, the i-th and the (i+1)th memory cells; wherein the data reading or programming operation for the i-th memory cell is performed by using the bit line and the control gate line connected to the (i+1)th memory cell in the block region which is different from the block region in which the i-th memory cell is located, when the i-th memory cell is in an end portion of the block region.

Claim 12

A method of driving a non-volatile semiconductor memory device comprising: providing a non-volatile semiconductor memory device which has: a memory cell array region in which are arranged a plurality of memory cells at least in a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; a plurality of bit lines extending in a column direction, each of the bit lines being connected to a connect line which connects two of the memory cells adjacent to each other in the row direction; a word line which is connected to the word gates of the memory cells arranged in the row direction; and a plurality of control gate lines each of which is connected to the first and second control gates respectively provided in adjacent two memory cells with the connect line interposed, the memory cell array region being divided into a plurality of block regions in the row direction corresponding to the I/O lines, and each of the block regions including 2 N memory cells; and performing a data reading or programming operation for one of the first and second non-volatile memory elements in the i-th memory cell in the row direction by using the word line, four of the bit lines, and four of the control gate lines connected to the (i−1)th, the i-th and the (i+1)th memory cells; wherein the data reading or programming operation for the i-th memory cell is performed by using the bit line and the control gate line connected to the (i+1)th memory cell in the block region which is different from the block region in which the i-th memory cell is located, when the i-th memory cell is in an end portion of the block region.