Push-pull output stage of integrated circuit providing enhanced high-low voltage level signal transition with ground bounce control

Claim 1

A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal susceptible to high switching speeds wherein the high-low voltage level transition of the signal during the operation of the integrated circuit is achieved while inhibiting the overshoot of the pulse-like signal leading to inaccurate interpretation of the pulse-like signal as to the voltage level thereof, said push-pull output stage comprising: a first plurality of output field-effect transistors having respective source and drain regions and gate electrodes extending therebetween, said first plurality of output field-effect transistors being connected in parallel and defining a first group of subtransistors; a second plurality of output field-effect transistors of opposite channel polarity with respect to said first plurality of output field-effect transistors and having respective source and drain regions and gate electrodes extending therebetween, said second plurality of output field-effect transistors being connected in parallel and defining a second group of subtransistors; each of said subtransistors of said first group of subtransistors being connected in series to the corresponding subtransistors of said second group of subtransistors; an input terminal for receiving the input signal and connected to said first and second groups of subtransistors; switching means interposed in the connection between said input terminal and each of said first and second groups of subtransistors to alternatively render said first and second groups of subtransistors conductive and nonconductive in response to the logic state of the input signal at a high voltage level or a low voltage level; an output line connected between each subtransistor of said first group of subtransistors and the corresponding subtransistor of said second group of subtransistors and terminating in an output terminal from which the output signal is produced; a resistance element connected to the gate electrode of each of the subtransistors of each of said first and second groups of subtransistors; the resistance elements connected between the gage electrodes of consecutive subtransistors of each of said first and second groups of subtransistors respectively comprising a pair of complementary parallel-connected field-effect transistors; a disconnecting field-effect transistor connected to each subtransistor of each of said first and second groups of subtransistors; and a control field-effect transistor connected in parallel to each of said first and second groups of subtransistors, each said control field-effect transistor being of opposite channel polarity with respect to the subtransistors of the group of subtransistors to which the respective control field-effect transistor is connected in parallel, each said control field-effect transistor being connected with respect to the input signal and the output signal as a source follower.