Method of packaging microwave semiconductor components and integrated circuits

Claim 1

A method of packaging gallium arsenide monolithic microwave integrated circuits (MMICs), comprising: (i) etching recesses in a first major surface of a silicon motherboard (SMB); (ii) etching vias at least from a second major surface of said SMB to a bottom of said recesses; and (iii) depositing said MMICs in said recesses; wherein said SMB comprises silicon having a resistivity of at least 8 kΩ cm and being operable to conduct energy at RF frequencies.

Claim 2

A method of packaging gallium arsenide monolithic microwave integrated circuits (MMICs), comprising: (i) etching recesses in a first major surface of a silicon motherboard (SMB); (ii) etching vias at least from a second major surface of said SMB to a bottom of said recesses; and (iii) depositing said MMICs in said recesses; wherein said SMB comprises silicon having a resistivity of at least 8 kΩ cm and being operable to conduct energy at RF frequencies.

Claim 13

A method of packaging gallium arsenide monolithic microwave integrated circuits (MMICs), comprising: (i) thermally oxidizing first and second major surfaces of an ultra high purity, uncompensated silicon substrate at a temperature greater than >1000° C. in a wet atmosphere to provide an oxide layer; (ii) sputtering a gold film onto said second major surface of said substrate; (iii) etching said first major surface using photolithographic techniques, to open up selected areas on said first major surface; (iv) anisotropically etching said selected areas of said first major surface to form device recesses and vias, by placing said substrate in a solution of KOH and water at a temperature of approximately 85° C. in a reflux etching system; (v) depositing a thin layer of amorphous silicon on said first major surface, and covering said thin layer of amorphous silicon with a plasma enhanced chemical vapor deposited (PECVD) layer of silicon dioxide, followed by tantalum nitride, titanium-tungsten, and gold in that order; (vi) removing said gold layer from said second major surface, and forming additional vias in said second major surface by etching said silicon on a side of said second major surface to a depth of one-half of the thickness of the substrate; (vii) sputtering another thin film of gold on said second major surface, patterning said first major surface with photoresist to expose baseplates of capacitors, said additional vias, and bottoms of device recesses, followed by electroplating said substrate with gold; (viii) reactive ion etching said tantalum nitride layer; (ix) depositing a PECVD layer of silicon nitride which then is photoresist coated, patterned, and etched to form capacitor dielectric and cross-protection for air bridges; and (x) depositing a plating conductivity layer over a pre-patterned photoresist layer, and placing and patterning a second resist layer, followed by electroplating of said substrate, so as to form the capacitor top plates, inductors, resistor terminations, and air bridges.

Claim 14

A method of packaging gallium arsenide monolithic microwave integrated circuits (MMICs), comprising: (i) thermally oxidizing first and second major surfaces of an ultra high purity, uncompensated silicon substrate at a temperature greater than >1000° C. in a wet atmosphere to provide an oxide layer; (ii) sputtering a gold film onto said second major surface of said substrate; (iii) etching said first major surface using photolithographic techniques, to open up selected areas on said first major surface; (iv) anisotropically etching said selected areas of said first major surface to form device recesses and vias, by placing said substrate in a solution of KOH and water at a temperature of approximately 85° C. in a reflux etching system; (v) depositing a thin layer of amorphous silicon on said first major surface, and covering said thin layer of amorphous silicon with a plasma enhanced chemical vapor deposited (PECVD) layer of silicon dioxide, followed by tantalum nitride, titanium-tungsten, and gold in that order; (vi) removing said gold layer from said second major surface, and forming additional vias in said second major surface by etching said silicon on a side of said second major surface to a depth of one-half of the thickness of the substrate; (vii) sputtering another thin film of gold on said second major surface, patterning said first major surface with photoresist to expose baseplates of capacitors, said additional vias, and bottoms of device recesses, followed by electroplating said substrate with gold; (viii) reactive ion etching said tantalum nitride layer; (ix) depositing a PECVD layer of silicon nitride which then is photoresist coated, patterned, and etched to form capacitor dielectric and cross-protection for air bridges; and (x) depositing a plating conductivity layer over a pre-patterned photoresist layer, and placing and patterning a second resist layer, followed by electroplating of said substrate, so as to form the capacitor top plates, inductors, resistor terminations, and air bridges.