Patent US5567964A successfully refreshed from Google Patents.
US5567964A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1995-09-11
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Granted: 1996-10-22
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Expires: 2015-09-11
Abstract
Abstract An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.
Inventors
- 👤 Keiichiro Kashihara
- 👤 Hiromi Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:32
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B53/00; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a conductive region formed in the main surface of said semiconductor substrate; an insulating layer formed on the main surface of said semiconductor substrate and covering said conductive region, said insulating layer having a hole extending from a top surface of said insulating layer and reaching a surface of said conductive region; a lower electrode layer formed on the top surface of said insulating layer to be connected electrically to said conductive region through said hole; a capacitor insulating layer including a high permittivity dielectric material and formed only on said lower electrode layer; a sidewall insulating layer covering at least a sidewall surface of said lower electrode layer; and an upper electrode layer formed directly on said capacitor insulating layer and directly on said sidewall insulating layer and covering said lower electrode layer; wherein the capacitor insulating layer is formed of a material different from that of the sidewall insulating layer.
Claim 2
Dependent Claim
163 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a conductive region formed in the main surface of said semiconductor substrate; an insulating layer formed on the main surface of said semiconductor substrate and covering said conductive region, said insulating layer having a hole extending from a top surface of said insulating layer and reaching a surface of said conductive region; a lower electrode layer formed on the top surface of said insulating layer to be connected electrically to said conductive region through said hole; a capacitor insulating layer including a high permittivity dielectric material and formed only on said lower electrode layer; a sidewall insulating layer covering at least a sidewall surface of said lower electrode layer; and an upper electrode layer formed directly on said capacitor insulating layer and directly on said sidewall insulating layer and covering said lower electrode layer; wherein the capacitor insulating layer is formed of a material different from that of the sidewall insulating layer.
Claim 3
Dependent Claim
42 words
The semiconductor device according to claim 1, wherein said sidewall insulating layer has a portion formed directly on the top surface of said insulating layer, which portion extends upward from the top surface of said insulating layer with its width reduced continuously.
Claim 4
Dependent Claim
16 words
The semiconductor device according to claim 1, wherein said high permittivity dielectric material is paraelectric material.
Claim 5
Dependent Claim
17 words
The semiconductor device according to claim 1, wherein said sidewall insulating layer includes a silicon oxide film.
Claim 6
Dependent Claim
34 words
The semiconductor device according to claim 1, wherein said sidewall insulating layer is made of a material selected from the group consisting of ZrO 2 , TiO 2 and Ta 2 O 5 .
Claim 7
Dependent Claim
19 words
The semiconductor device according to claim 1, wherein said conductive region is a source/drain region of an MOS transistor.
Claim 8
Dependent Claim
35 words
The semiconductor device according to claim 1, wherein said lower electrode layer includes a layer made of at least a material selected from the group consisting of Pt (platinum), Pd (palladium) and RuO 2 .
Claim 9
Dependent Claim
41 words
The semiconductor device according to claim 1, wherein said upper electrode layer includes a layer made of at least a material selected from the group consisting of Pt (platinum), doped polysilicon, Al (aluminum), Ti (titanium), TiN (titanium nitride) and W (tungsten).
Claim 10
Dependent Claim
50 words
The semiconductor device according to claim 1, wherein said high permittivity dielectric material is made of at least a material selected from the group consisting of lead titanate zirconate (PZT), lanthan-doped lead titanate zirconate (PLZT), strontium titanate (ST), barium strontium titanate (BST) and tantalum oxide (Ta 2 O 5 ).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |