Patent US2647025A successfully refreshed from Google Patents.
Patent US5625602A successfully refreshed from Google Patents.
US5625602A
Expired / Lapsed
US
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NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
Assignee: Toshiba Corp
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Filing: 1995-05-22
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Granted: 1997-04-29
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Expires: 2015-05-22
Abstract
Abstract A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
Inventors
- 👤 Takehiro Hasegawa
- 👤 Yukihito Oowaki
- 👤 Fujio Masuoka
- 👤 Ryu Ogiwara
- 👤 Shinichiro Shiratake
- 👤 Shigeyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4045; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/4097; G11C7/1078
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
A dynamic semiconductor memory device comprising: a first bit line; a plurality of memory cell arrays each constructed by a plurality of memory cells which are connected to said first bit line; a first transfer gate connected to said first bit line; at least one sense amplifier arranged between adjacent memory cell arrays and having a first data node and a second data node, said first data node being connected selectively to at least two bit lines in one memory cell array of said adjacent memory cell arrays; at least one register arranged between said sense amplifier and said memory cell arrays and connected to at least one of said first data node and said second data node directly or via the second transfer gate, for temporarily storing memory cell data read out from a memory cell; and gate control means for controlling said first transfer gate to selectively connect to said first data node of said sense amplifier with said first bit line after activation of said sense amplifier, for writing the data from said register to said memory cell.
Claim 2
Dependent Claim
181 words
A dynamic semiconductor memory device comprising: a first bit line; a plurality of memory cell arrays each constructed by a plurality of memory cells which are connected to said first bit line; a first transfer gate connected to said first bit line; at least one sense amplifier arranged between adjacent memory cell arrays and having a first data node and a second data node, said first data node being connected selectively to at least two bit lines in one memory cell array of said adjacent memory cell arrays; at least one register arranged between said sense amplifier and said memory cell arrays and connected to at least one of said first data node and said second data node directly or via the second transfer gate, for temporarily storing memory cell data read out from a memory cell; and gate control means for controlling said first transfer gate to selectively connect to said first data node of said sense amplifier with said first bit line after activation of said sense amplifier, for writing the data from said register to said memory cell.
Claim 3
Dependent Claim
28 words
A dynamic semiconductor memory device, according to claim 1, wherein each of said registers is constructed by memory cells being the same as the said memory cell arrays.
Claim 4
Dependent Claim
31 words
A dynamic semiconductor memory device, according to claim 1, wherein each of said register is constructed by the memory cells each of which is composed of one transistor and one capacitor.
Claim 5
Dependent Claim
193 words
A dynamic semiconductor memory device comprising: a first bit line; a plurality of memory cell arrays each constructed by a plurality of memory cells which are connected to said first bit line and which are each formed of a plurality of series-connected dynamic memory cells; a first transfer gate connected to said first bit line; at least one sense amplifier arranged between adjacent memory cell arrays and having a first data node and a second data node, said first data node being connected selectively to at least two bit lines in one memory cell array of said adjacent memory cell arrays; at least one register arranged between said sense amplifier and said memory cell arrays and connected to at least one of said first data node and said second data node directly or via a second transfer gate, for temporarily storing memory cell data read out from the memory cell; and gate control means for controlling said first transfer gate to selectively connect said first data node of said sense amplifier with said first bit line after activation of said sense amplifier, for writing the data from said register to said memory cell.
Claim 6
Dependent Claim
193 words
A dynamic semiconductor memory device comprising: a first bit line; a plurality of memory cell arrays each constructed by a plurality of memory cells which are connected to said first bit line and which are each formed of a plurality of series-connected dynamic memory cells; a first transfer gate connected to said first bit line; at least one sense amplifier arranged between adjacent memory cell arrays and having a first data node and a second data node, said first data node being connected selectively to at least two bit lines in one memory cell array of said adjacent memory cell arrays; at least one register arranged between said sense amplifier and said memory cell arrays and connected to at least one of said first data node and said second data node directly or via a second transfer gate, for temporarily storing memory cell data read out from the memory cell; and gate control means for controlling said first transfer gate to selectively connect said first data node of said sense amplifier with said first bit line after activation of said sense amplifier, for writing the data from said register to said memory cell.
Claim 7
Dependent Claim
28 words
A dynamic semiconductor memory device, according to claim 4, wherein each of said registers is constructed by memory cells being the same as the said memory cell array.
Claim 8
Dependent Claim
31 words
A dynamic semiconductor memory device, according to claim 4, wherein each of said register is constructed by the memory cells each of which is composed of one transistor and one capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |