Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width

Claim 1

A method for programming a floating gate memory cell, comprising: applying a first program pulse to the cell having a first pulse height and a first pulse width selected so that the cell is unlikely to be over-programmed; determining whether the cell is programmed in response to the first program pulse; and if not applying a program retry pulse to the cell; determining whether the cell is programmed in response to the program retry pulse; and if not iteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is determined to be programmed or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height, the pattern selected so that the cell is likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries.

Claim 2

A method for programming a floating gate memory cell, comprising: applying a first program pulse to the cell having a first pulse height and a first pulse width selected so that the cell is unlikely to be over-programmed; determining whether the cell is programmed in response to the first program pulse; and if not applying a program retry pulse to the cell; determining whether the cell is programmed in response to the program retry pulse; and if not iteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is determined to be programmed or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height, the pattern selected so that the cell is likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries.

Claim 7

An apparatus for storing data, comprising: a memory array having a plurality of floating gate cells; supply circuits, coupled to the memory array, which apply voltages to the plurality of floating gate cells to program the plurality of floating gate cells in the memory cells; a plurality of bit latches, coupled to bit lines in the memory array, which bit latches provide a buffer for temporary storage of sata values to be programmed at least a portion of a row of floating gate cells in the memory array; and automatic program circuits, coupled to the memory array, the supply circuits and the plurality of bit latches, which program cells on a selected wordline and on bit lines coupled to a bit latch storing a program value, including circuitry to apply a first program pulse having a first pulse height and a first pulse width set so that the cells are unlikely to be over-programmed; to determine whether the cell is programmed in response to the first program pulse; and if it is, to reset the corresponding bit latch, and if it is not to apply a program retry pulse to the cell; to determine whether the cell is programmed in response to the program retry pulse; and if it is, to reset the corresponding bit latch and if it is not to interatively apply another program retry pulse to the cell, determine whether the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made; wherein the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.

Claim 8

An apparatus for storing data, comprising: a memory array having a plurality of floating gate cells; supply circuits, coupled to the memory array, which apply voltages to the plurality of floating gate cells to program the plurality of floating gate cells in the memory cells; a plurality of bit latches, coupled to bit lines in the memory array, which bit latches provide a buffer for temporary storage of sata values to be programmed at least a portion of a row of floating gate cells in the memory array; and automatic program circuits, coupled to the memory array, the supply circuits and the plurality of bit latches, which program cells on a selected wordline and on bit lines coupled to a bit latch storing a program value, including circuitry to apply a first program pulse having a first pulse height and a first pulse width set so that the cells are unlikely to be over-programmed; to determine whether the cell is programmed in response to the first program pulse; and if it is, to reset the corresponding bit latch, and if it is not to apply a program retry pulse to the cell; to determine whether the cell is programmed in response to the program retry pulse; and if it is, to reset the corresponding bit latch and if it is not to interatively apply another program retry pulse to the cell, determine whether the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made; wherein the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.

Claim 17

A method of storing data in a memory array on an integrated circuit having M rows and N columns of floating gate memory cells comprising the steps of: loading a page buffer on the integrated circuit with a row of input data; selecting a row of memory cells for programming the input data to the row of memory cells; applying a first program pulse to cells in the row of memory cells corresponding to input data having a program value in the page buffer; reading the row of memory cells to verify programming of the input data to the row of memory cells; resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and if data having a program value remains in the page buffer, then applying a program retry pulse to the cells in the row of memory cells corresponding to input data having a program value in the page buffer; reading the row of memory cells to verify programming of the input data to the row of memory cells; and resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and if data having a program value remains in the page buffer, then alternatively applying another program retry pulse to the cell and reading and resetting the input data for programmed cells, until the row is determined to be programmed or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.

Claim 18

A method of storing data in a memory array on an integrated circuit having M rows and N columns of floating gate memory cells comprising the steps of: loading a page buffer on the integrated circuit with a row of input data; selecting a row of memory cells for programming the input data to the row of memory cells; applying a first program pulse to cells in the row of memory cells corresponding to input data having a program value in the page buffer; reading the row of memory cells to verify programming of the input data to the row of memory cells; resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and if data having a program value remains in the page buffer, then applying a program retry pulse to the cells in the row of memory cells corresponding to input data having a program value in the page buffer; reading the row of memory cells to verify programming of the input data to the row of memory cells; and resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and if data having a program value remains in the page buffer, then alternatively applying another program retry pulse to the cell and reading and resetting the input data for programmed cells, until the row is determined to be programmed or a maximum number of retries is made; wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.